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m68hc08 microcontrollers freescale.com mc68hc908ab32 technical data rev. 1.1 mc68hc908ab32/d august 2, 2005

mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor list of sections 3 technical data ? mc68hc908ab32 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . 29 section 2. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . 41 section 3. random-a ccess memory (ram) . . . . . . . . . . 57 section 4. flash memory . . . . . . . . . . . . . . . . . . . . . . . . 59 section 5. eeprom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 section 6. configuration register (config) . . . . . . . . . 85 section 7. central processor unit (cpu) . . . . . . . . . . . . 89 section 8. system integration module (sim) . . . . . . . . 109 section 9. clock generator modu le (cgm) . . . . . . . . . . 131 section 10. monitor rom (mon) . . . . . . . . . . . . . . . . . . 157 section 11. timer interface modu le a (tima) . . . . . . . . 169 section 12. timer interface modu le b (timb) . . . . . . . . 195 section 13. programmable interr upt timer (pit) . . . . . 221 section 14. analog-to-digital converter (adc) . . . . . . 229 section 15. serial comm unications interface module (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 section 16. serial peripheral interface module (spi) . . 279 section 17. input/output (i/o) port s . . . . . . . . . . . . . . . 311 section 18. external interrupt (irq ) . . . . . . . . . . . . . . . 339 section 19. keyboard interrupt module (kbi). . . . . . . . 345
list of sections technical data mc68hc908ab32 ? rev. 1.1 4 list of sections freescale semiconductor section 20. computer operatin g properly (cop) . . . . 353 section 21. low-voltage inhibit (lvi) . . . . . . . . . . . . . . 359 section 22. break module (brk) . . . . . . . . . . . . . . . . . . 365 section 23. electrical sp ecifications. . . . . . . . . . . . . . . 373 section 24. mechanical specificati ons . . . . . . . . . . . . . 387 section 25. ordering in formation . . . . . . . . . . . . . . . . . 389
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor table of contents 5 technical data ? mc68hc908ab32 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 1.6.1 power supply pins (v dd and v ss ) . . . . . . . . . . . . . . . . . . . . 34 1.6.2 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . 35 1.6.3 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6.4 external interrupt pin (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6.5 analog power supply pin (v dda ) . . . . . . . . . . . . . . . . . . . . .35 1.6.6 analog ground pin (v ssa ) . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6.7 analog ground pin (a vss /v refl ). . . . . . . . . . . . . . . . . . . . .35 1.6.8 adc voltage reference pin (v refh ) . . . . . . . . . . . . . . . . . . 36 1.6.9 analog supply pin (v ddaref ) . . . . . . . . . . . . . . . . . . . . . . . 36 1.6.10 external filter capac itor pin (cgmxfc) . . . . . . . . . . . . . . . 36 1.6.11 port a input/output (i/o) pins (pta7?pta0) . . . . . . . . . . . . 36 1.6.12 port b i/o pins (ptb7/atd7?ptb 0/atd0) . . . . . . . . . . . . . 36 1.6.13 port c i/o pins (ptc5?p tc0) . . . . . . . . . . . . . . . . . . . . . . . 36 1.6.14 port d i/o pins (ptd7?p td0) . . . . . . . . . . . . . . . . . . . . . . . 37 1.6.15 port e i/o pins (pte7/spsck?pte0 /txd) . . . . . . . . . . . . . 37 1.6.16 port f i/o pins (ptf 7?ptf0/tach2) . . . . . . . . . . . . . . . . . 37 1.6.17 port g i/o pins (ptg2/kbd2?ptg 0/kbd0) . . . . . . . . . . . . 37 1.6.18 port h i/o pins (pth1/kbd4?pth0/ kbd3). . . . . . . . . . . . . 37 1.7 i/o pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.8 signal name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.9 clock source summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
table of contents technical data mc68hc908ab32 ? rev. 1.1 6 table of contents freescale semiconductor section 2. memory map 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3 unimplemented memory loc ations . . . . . . . . . . . . . . . . . . . . . 41 2.4 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.5 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 section 3. random-access memory (ram) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 section 4. flash memory 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 4.4 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.5 flash page erase operatio n . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.7 flash program/read operation . . . . . . . . . . . . . . . . . . . . . . . 63 4.8 flash block protecti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.8.1 flash block protect regi ster . . . . . . . . . . . . . . . . . . . . . . . 66 4.9 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.10 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 section 5. eeprom 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
table of contents mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor table of contents 7 5.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 5.5 eeprom configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.6 eeprom timebase requirem ents . . . . . . . . . . . . . . . . . . . . . 72 5.7 eeprom security options. . . . . . . . . . . . . . . . . . . . . . . . . . . .72 5.8 eeprom block protec tion . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 5.9 eeprom programming and er asing . . . . . . . . . . . . . . . . . . . . 73 5.9.1 eeprom programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 5.9.2 eeprom erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.10 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.10.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 5.10.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 5.11 eeprom registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.11.1 eeprom control register . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.11.2 eeprom array configur ation register . . . . . . . . . . . . . . . . 79 5.11.2.1 eeprom non-volatile register. . . . . . . . . . . . . . . . . . . . 80 5.11.3 eeprom timebase divider register . . . . . . . . . . . . . . . . . 80 5.11.3.1 eeprom timebase divider non-volatile register . . . . . 82 section 6. configurat ion register (config) 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3 functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.4 configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.5 configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 section 7. central pr ocessor unit (cpu) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
table of contents technical data mc68hc908ab32 ? rev. 1.1 8 table of contents freescale semiconductor 7.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 7.7 cpu during break interrupt s . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 section 8. system integration module (sim) 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . 112 8.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.3.2 clock start-up from por or lvi reset . . . . . . . . . . . . . . . 113 8.3.3 clocks in stop and wait modes . . . . . . . . . . . . . . . . . . . . . 113 8.4 reset and system initiali zation. . . . . . . . . . . . . . . . . . . . . . . . 113 8.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.4.2 active resets from in ternal sources . . . . . . . . . . . . . . . . . 114 8.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 8.4.2.2 computer operati ng properly (cop) rese t. . . . . . . . . . 116 8.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . .117 8.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . 117 8.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.5.1 sim counter during power-on rese t. . . . . . . . . . . . . . . . . 118 8.5.2 sim counter during stop mode re covery . . . . . . . . . . . . . 118 8.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . . 118
table of contents mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor table of contents 9 8.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 8.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.6.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.6.3 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.6.4 status flag protection in break mode . . . . . . . . . . . . . . . . 123 8.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 8.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 8.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 8.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.8.1 sim break status regi ster . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.8.2 sim reset status regi ster . . . . . . . . . . . . . . . . . . . . . . . . . 128 8.8.3 sim break flag control register . . . . . . . . . . . . . . . . . . . . 129 section 9. clock generator module (cgm) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 9.4.1 crystal oscillator circ uit . . . . . . . . . . . . . . . . . . . . . . . . . . .134 9.4.2 phase-locked loop (pll ) circuit . . . . . . . . . . . . . . . . . . . 135 9.4.2.1 pll circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.4.2.2 acquisition and tracking modes . . . . . . . . . . . . . . . . . . 136 9.4.2.3 manual and automatic pll b andwidth modes . . . . . . . 136 9.4.2.4 programming the pll . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.4.2.5 special programming exceptions . . . . . . . . . . . . . . . . . 139 9.4.3 base clock selector ci rcuit . . . . . . . . . . . . . . . . . . . . . . . . 140 9.4.4 cgm external connectio ns . . . . . . . . . . . . . . . . . . . . . . . . 140 9.5 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.5.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . 142 9.5.2 crystal amplifier ou tput pin (osc2) . . . . . . . . . . . . . . . . . 142 9.5.3 external filter capacitor pin (c gmxfc) . . . . . . . . . . . . . . 142 9.5.4 pll analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . . 142
table of contents technical data mc68hc908ab32 ? rev. 1.1 10 table of contents freescale semiconductor 9.5.5 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . 142 9.5.6 crystal output frequency signal (cgmxclk) . . . . . . . . . 143 9.5.7 cgm base clock output (cgmout) . . . . . . . . . . . . . . . . . 143 9.5.8 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . . 143 9.6 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.6.1 pll control register (pctl) . . . . . . . . . . . . . . . . . . . . . . . 144 9.6.2 pll bandwidth control register (pbwc) . . . . . . . . . . . . . 146 9.6.3 pll programming regi ster (ppg) . . . . . . . . . . . . . . . . . . . 148 9.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 9.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 9.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 9.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 9.9 cgm during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.10 acquisition/lock time spec ifications . . . . . . . . . . . . . . . . . . . 151 9.10.1 acquisition/lock time definitions. . . . . . . . . . . . . . . . . . . .152 9.10.2 parametric influences on reacti on time. . . . . . . . . . . . . . 153 9.10.3 choosing a filter capac itor . . . . . . . . . . . . . . . . . . . . . . . . 154 9.10.4 reaction time calculat ion . . . . . . . . . . . . . . . . . . . . . . . . . 155 section 10. monitor rom (mon) 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 10.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 10.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 10.4.3 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 10.4.4 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 10.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 10.4.6 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 10.5 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 10.6 extended security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
table of contents mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor table of contents 11 section 11. timer inte rface module a (tima) 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 11.5.1 tima counter prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . .171 11.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 11.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 175 11.5.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .176 11.5.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 177 11.5.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 178 11.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 179 11.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 11.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 11.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 11.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 11.8 tima during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . . 182 11.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 11.9.1 tima clock pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 11.9.2 tima channel i/o pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 11.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 11.10.1 tima status an d control register . . . . . . . . . . . . . . . . . . . 184 11.10.2 tima counter registers. . . . . . . . . . . . . . . . . . . . . . . . . . .186 11.10.3 tima counter modulo registers . . . . . . . . . . . . . . . . . . . . 187 11.10.4 tima channel status and control registers . . . . . . . . . . . 188 11.10.5 tima channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . 192
table of contents technical data mc68hc908ab32 ? rev. 1.1 12 table of contents freescale semiconductor section 12. timer inte rface module b (timb) 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 12.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 12.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 12.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 12.5.1 timb counter prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . .197 12.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 12.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 12.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 201 12.5.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .202 12.5.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 203 12.5.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 204 12.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 205 12.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 12.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 12.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 12.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 12.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 12.8 timb during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . . 208 12.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 12.9.1 timb clock pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 12.9.2 timb channel i/o pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 12.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12.10.1 timb status an d control register . . . . . . . . . . . . . . . . . . . 210 12.10.2 timb counter registers. . . . . . . . . . . . . . . . . . . . . . . . . . .212 12.10.3 timb counter modulo registers . . . . . . . . . . . . . . . . . . . . 213 12.10.4 timb channel status and control registers . . . . . . . . . . . 214 12.10.5 timb channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . 218
table of contents mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor table of contents 13 section 13. programmable interrupt timer (pit) 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 13.4.1 pit counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 13.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 13.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 13.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 13.6 pit during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 224 13.7 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 13.7.1 pit status and control register. . . . . . . . . . . . . . . . . . . . . 225 13.7.2 pit counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 13.7.3 pit counter modulo registers . . . . . . . . . . . . . . . . . . . . . . 228 section 14. analog-to-dig ital converter (adc) 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 14.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 14.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 14.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 14.4.4 conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 14.4.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 14.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 14.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 14.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.7.1 adc analog power pin (v ddaref ). . . . . . . . . . . . . . . . . . . 234
table of contents technical data mc68hc908ab32 ? rev. 1.1 14 table of contents freescale semiconductor 14.7.2 adc analog ground pin (a vss /v refl ) . . . . . . . . . . . . . . . 234 14.7.3 adc voltage reference high pin (v refh ). . . . . . . . . . . . . 234 14.7.4 adc voltage in (v adin ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 14.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 14.8.1 adc status and control register (adscr). . . . . . . . . . . . 235 14.8.2 adc data register ( adr) . . . . . . . . . . . . . . . . . . . . . . . . . 237 14.8.3 adc clock register (a dclk) . . . . . . . . . . . . . . . . . . . . . . 237 section 15. serial communications interface module (sci) 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .239 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 15.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 15.5.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 15.5.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 15.5.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 15.5.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . 247 15.5.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 15.5.2.4 idle characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 15.5.2.5 inversion of transm itted output. . . . . . . . . . . . . . . . . . . 249 15.5.2.6 transmitter in terrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .249 15.5.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 15.5.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 15.5.3.2 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 15.5.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 15.5.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 15.5.3.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .254 15.5.3.6 receiver wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 15.5.3.7 receiver interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 15.5.3.8 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 15.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 15.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259
table of contents mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor table of contents 15 15.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 15.7 sci during break module interrupts. . . . . . . . . . . . . . . . . . . .260 15.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 15.8.1 pte0/txd (transmit data). . . . . . . . . . . . . . . . . . . . . . . . . 260 15.8.2 pte1/rxd (receive data ) . . . . . . . . . . . . . . . . . . . . . . . . . 260 15.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 15.9.1 sci control regi ster 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 15.9.2 sci control regi ster 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 15.9.3 sci control regi ster 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 15.9.4 sci status register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 15.9.5 sci status register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 15.9.6 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 15.9.7 sci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . .275 section 16. serial peripher al interface module (spi) 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 16.4 pin name conventions and i/o r egister addresses . . . . . . . 281 16.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 16.5.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 16.5.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 16.6 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285 16.6.1 clock phase and polarity controls. . . . . . . . . . . . . . . . . . . 285 16.6.2 transmission format wh en cpha = 0 . . . . . . . . . . . . . . . 286 16.6.3 transmission format wh en cpha = 1 . . . . . . . . . . . . . . . 288 16.6.4 transmission initiation latency . . . . . . . . . . . . . . . . . . . . . 289 16.7 queuing transmissi on data . . . . . . . . . . . . . . . . . . . . . . . . . . 291 16.8 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 16.8.1 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 16.8.2 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 16.9 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296
table of contents technical data mc68hc908ab32 ? rev. 1.1 16 table of contents freescale semiconductor 16.10 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 16.11 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 16.11.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299 16.11.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299 16.12 spi during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 300 16.13 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 16.13.1 miso (master in/slave out) . . . . . . . . . . . . . . . . . . . . . . . . 301 16.13.2 mosi (master out/slave in) . . . . . . . . . . . . . . . . . . . . . . . . 301 16.13.3 spsck (serial clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 16.13.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 16.13.5 cgnd (clock ground ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 16.14 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 16.14.1 spi control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 16.14.2 spi status and control register . . . . . . . . . . . . . . . . . . . . 306 16.14.3 spi data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 section 17. input/output (i/o) ports 17.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 17.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 17.3.1 port a data register (pta) . . . . . . . . . . . . . . . . . . . . . . . . 316 17.3.2 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . 316 17.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 17.4.1 port b data register (ptb) . . . . . . . . . . . . . . . . . . . . . . . . 318 17.4.2 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . 319 17.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 17.5.1 port c data register (ptc) . . . . . . . . . . . . . . . . . . . . . . . . 320 17.5.2 data direction register c (ddrc). . . . . . . . . . . . . . . . . . . 321 17.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 17.6.1 port d data register (ptd) . . . . . . . . . . . . . . . . . . . . . . . . 323 17.6.2 data direction register d (ddrd). . . . . . . . . . . . . . . . . . . 324 17.6.3 port d input pullup enable register (ptdp ue). . . . . . . . . 325
table of contents mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor table of contents 17 17.7 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 17.7.1 port e data register (pte) . . . . . . . . . . . . . . . . . . . . . . . . 326 17.7.2 data direction register e (ddre) . . . . . . . . . . . . . . . . . . . 328 17.8 port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 17.8.1 port f data register (ptf) . . . . . . . . . . . . . . . . . . . . . . . . 329 17.8.2 data direction register f (ddrf) . . . . . . . . . . . . . . . . . . . 330 17.8.3 port f input pullup enable regi ster (ptfpue) . . . . . . . . . 332 17.9 port g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 17.9.1 port g data register (ptg) . . . . . . . . . . . . . . . . . . . . . . . . 332 17.9.2 data direction register g (ddrg) . . . . . . . . . . . . . . . . . . 333 17.10 port h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 17.10.1 port h data register (pth) . . . . . . . . . . . . . . . . . . . . . . . . 335 17.10.2 data direction register h (ddrh). . . . . . . . . . . . . . . . . . . 335 section 18. external interrupt (irq) 18.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340 18.4.1 irq pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 18.5 irq status and control register (iscr) . . . . . . . . . . . . . . . . 343 18.6 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 344 section 19. keyboard in terrupt module (kbi) 19.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .345 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 19.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 19.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 19.5.1 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 19.5.2 keyboard status and control register. . . . . . . . . . . . . . . . 349
table of contents technical data mc68hc908ab32 ? rev. 1.1 18 table of contents freescale semiconductor 19.5.3 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 351 19.6 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 19.7 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 19.8 keyboard module during break interrupts . . . . . . . . . . . . . . . 352 section 20. computer op erating properly (cop) 20.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .353 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 20.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354 20.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 20.4.1 cgmxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355 20.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 20.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355 20.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 20.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 20.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 20.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 20.4.8 coprs (cop rate sele ct) . . . . . . . . . . . . . . . . . . . . . . . . 356 20.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 20.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 20.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 20.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 20.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 20.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 20.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 358 section 21. low-volt age inhibit (lvi) 21.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .359 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 21.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
table of contents mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor table of contents 19 21.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .360 21.4.1 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 21.4.2 forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . .361 21.4.3 false reset protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 21.5 lvi status register (lvisr) . . . . . . . . . . . . . . . . . . . . . . . . . . 362 21.6 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362 21.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 21.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363 21.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363 section 22. break module (brk) 22.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 22.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 22.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366 22.4.1 flag protection during break interr upts . . . . . . . . . . . . . . . 368 22.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . .368 22.4.3 pit, tima, and timb during break interrupts . . . . . . . . . . 368 22.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 368 22.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 22.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368 22.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369 22.6 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 22.6.1 break status and control register. . . . . . . . . . . . . . . . . . . 369 22.6.2 break address register s . . . . . . . . . . . . . . . . . . . . . . . . . . 370 22.6.3 sim break status regi ster . . . . . . . . . . . . . . . . . . . . . . . . . 370 22.6.4 sim break flag control register . . . . . . . . . . . . . . . . . . . . 372 section 23. electrical specifications 23.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 23.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 374
table of contents technical data mc68hc908ab32 ? rev. 1.1 20 table of contents freescale semiconductor 23.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 375 23.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 23.6 5.0-v dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . 376 23.7 eeprom and memory characteristics . . . . . . . . . . . . . . . . . 377 23.8 5.0-v control timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 23.9 timer interface module characteristics . . . . . . . . . . . . . . . . . 378 23.10 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 23.11 spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 23.12 clock generation module characteristics . . . . . . . . . . . . . . . 383 23.12.1 cgm operating condition s . . . . . . . . . . . . . . . . . . . . . . . . 383 23.12.2 cgm component informat ion . . . . . . . . . . . . . . . . . . . . . . 383 23.12.3 cgm acquisition/lock time inform ation . . . . . . . . . . . . . . 384 23.13 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . 385 section 24. mechanic al specifications 24.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387 24.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 24.3 64-pin plastic quad flat pack (qfp) . . . . . . . . . . . . . . . . . . . 388 section 25. ordering information 25.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .389 25.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 25.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor list of figures 21 technical data ? mc68hc908ab32 list of figures figure title page 1-1 mc68hc908ab32 block diagram . . . . . . . . . . . . . . . . . . . . . . 32 1-2 64-pin qfp pin assi gnment . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1-3 power supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2-1 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2-2 control, status, and data registers . . . . . . . . . . . . . . . . . . . . .45 4-1 flash control regist er (flcr) . . . . . . . . . . . . . . . . . . . . . . . 60 4-2 flash programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . 65 4-4 flash block protec t start address . . . . . . . . . . . . . . . . . . . . .66 4-3 flash block protect register (flbpr). . . . . . . . . . . . . . . . . . 66 5-1 eeprom i/o register summ ary . . . . . . . . . . . . . . . . . . . . . . . 70 5-2 eeprom control register (eecr) . . . . . . . . . . . . . . . . . . . . . 77 5-3 eeprom array configur ation register (eeacr) . . . . . . . . . . 79 5-4 eeprom non-volatile re gister (eenvr) . . . . . . . . . . . . . . . . 80 5-5 eeprom divider register high (eedi vh) . . . . . . . . . . . . . . . 81 5-6 eeprom divider r egister low (eedivl) . . . . . . . . . . . . . . . . 81 5-7 eeprom divider non-volatile register high(eedivhnvr) . . 82 5-8 eeprom divider non-volatile register low (eedivlnvr) . . 82 6-1 configuration register 1 (config1) . . . . . . . . . . . . . . . . . . . . 86 6-2 configuration register 2 (config2) . . . . . . . . . . . . . . . . . . . . 88 7-1 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7-2 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7-3 index register (h:x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7-4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7-5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 7-6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . 94
list of figures technical data mc68hc908ab32 ? rev. 1.1 22 list of figures freescale semiconductor figure title page 8-1 sim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8-2 sim i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . .112 8-3 cgm clock signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 8-4 external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 8-5 internal reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8-6 sources of internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 8-7 por recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 8-8 interrupt entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8-9 interrupt recovery timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8-10 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8-11 interrupt recognition example . . . . . . . . . . . . . . . . . . . . . . . . 121 8-12 wait mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 8-13 wait recovery from interrupt or br eak . . . . . . . . . . . . . . . . . . 125 8-14 wait recovery from internal reset. . . . . . . . . . . . . . . . . . . . . 125 8-15 stop mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 8-16 stop mode recovery fr om interrupt or break . . . . . . . . . . . . . 126 8-17 sim break status regist er (sbsr) . . . . . . . . . . . . . . . . . . . . 127 8-18 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . . . 128 8-19 sim break flag control register (s bfcr) . . . . . . . . . . . . . . 129 9-1 cgm block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 9-2 cgm i/o register summar y. . . . . . . . . . . . . . . . . . . . . . . . . . 134 9-3 cgm external connections . . . . . . . . . . . . . . . . . . . . . . . . . . 141 9-4 cgm i/o register summar y. . . . . . . . . . . . . . . . . . . . . . . . . . 144 9-5 pll control register (pc tl) . . . . . . . . . . . . . . . . . . . . . . . . . 144 9-7 pll bandwidth control register (pbwc) . . . . . . . . . . . . . . . 146 9-8 pll programming register (ppg) . . . . . . . . . . . . . . . . . . . . . 148 10-1 monitor mode circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 10-2 monitor data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 10-3 sample monitor waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 161 10-4 read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 10-5 break transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 10-6 monitor mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . .167 11-1 tima block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
list of figures mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor list of figures 23 figure title page 11-2 tima i/o register summar y. . . . . . . . . . . . . . . . . . . . . . . . . . 173 11-3 pwm period and pulse wi dth . . . . . . . . . . . . . . . . . . . . . . . . 177 11-4 tima status and contro l register (tasc) . . . . . . . . . . . . . . . 184 11-5 tima counter register high (tacnth). . . . . . . . . . . . . . . . . 186 11-6 tima counter register low (tacntl) . . . . . . . . . . . . . . . . . 187 11-7 tima counter modulo register high (tamodh). . . . . . . . . . 187 11-8 tima counter modulo register lo w (tamodl) . . . . . . . . . . 187 11-9 tima channel 0 status and contro l register (tasc0) . . . . . 188 11-10 tima channel 1 status and cont rol register (tasc1) . . . . . 188 11-11 tima channel 2 status and cont rol register (tasc2) . . . . . 189 11-12 tima channel 3 status and cont rol register (tasc3) . . . . . 189 11-13. chxmax latenc y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 11-14 tima channel 0 register high (tach 0h) . . . . . . . . . . . . . . . 192 11-15 tima channel 0 register low (ta ch0l). . . . . . . . . . . . . . . . 192 11-16 tima channel 1 register high (tach 1h) . . . . . . . . . . . . . . . 193 11-17 tima channel 1 register low (ta ch1l). . . . . . . . . . . . . . . . 193 11-18 tima channel 2 register high (tach 2h) . . . . . . . . . . . . . . . 193 11-19 tima channel 2 register low (ta ch2l). . . . . . . . . . . . . . . . 193 11-20 tima channel 3 register high (tach 3h) . . . . . . . . . . . . . . . 194 11-21 tima channel 3 register low (ta ch3l). . . . . . . . . . . . . . . . 194 12-1 timb block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 12-2 timb i/o register summar y. . . . . . . . . . . . . . . . . . . . . . . . . . 199 12-3 pwm period and pulse wi dth . . . . . . . . . . . . . . . . . . . . . . . . 203 12-4 timb status and contro l register (tbsc) . . . . . . . . . . . . . . . 210 12-5 timb counter register high (tbcnth). . . . . . . . . . . . . . . . . 212 12-6 timb counter register low (tbcntl) . . . . . . . . . . . . . . . . . 213 12-7 timb counter modulo register high (tbmodh). . . . . . . . . . 213 12-8 timb counter modulo register lo w (tbmodl) . . . . . . . . . . 213 12-9 timb channel 0 status and contro l register (tbsc0) . . . . . 214 12-10 timb channel 1 status and cont rol register (tbsc1) . . . . . 214 12-11 timb channel 2 status and cont rol register (tbsc2) . . . . . 215 12-12 timb channel 3 status and cont rol register (tbsc3) . . . . . 215 12-13. chxmax latenc y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 12-14 timb channel 0 register high (tbch 0h) . . . . . . . . . . . . . . . 218 12-15 timb channel 0 register low (tb ch0l). . . . . . . . . . . . . . . . 218
list of figures technical data mc68hc908ab32 ? rev. 1.1 24 list of figures freescale semiconductor figure title page 12-16 timb channel 1 register high (tbch 1h) . . . . . . . . . . . . . . . 219 12-17 timb channel 1 register low (tb ch1l). . . . . . . . . . . . . . . . 219 12-18 timb channel 2 register high (tbch 2h) . . . . . . . . . . . . . . . 219 12-19 timb channel 2 register low (tb ch2l). . . . . . . . . . . . . . . . 219 12-20 timb channel 3 register high (tbch 3h) . . . . . . . . . . . . . . . 220 12-21 timb channel 3 register low (tb ch3l). . . . . . . . . . . . . . . . 220 13-1 pit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 13-2 pit i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 13-3 pit status and control register (psc) . . . . . . . . . . . . . . . . . 225 13-4 pit counter register high (pcnth) . . . . . . . . . . . . . . . . . . . 227 13-5 pit counter register low (pcntl) . . . . . . . . . . . . . . . . . . . .228 13-6 pit counter modulo re gister high (pmodh) . . . . . . . . . . . . 228 13-7 pit counter modulo re gister low (pmodl) . . . . . . . . . . . . . 228 14-1 adc register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 14-2 adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 14-3 adc status and control register (adscr) . . . . . . . . . . . . . . 235 14-4 adc data register (adr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 14-5 adc clock register (adc lk) . . . . . . . . . . . . . . . . . . . . . . . . 237 15-1 sci module block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .243 15-2 sci i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . .244 15-3 sci data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 15-4 sci transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 15-5 sci receiver block diagr am . . . . . . . . . . . . . . . . . . . . . . . . . 251 15-6 receiver data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 15-7 slow data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 15-8 fast data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 15-9 sci control regist er 1 (scc1). . . . . . . . . . . . . . . . . . . . . . . . 262 15-10 sci control regist er 2 (scc2). . . . . . . . . . . . . . . . . . . . . . . . 265 15-11 sci control regist er 3 (scc3). . . . . . . . . . . . . . . . . . . . . . . . 267 15-12 sci status register 1 (s cs1) . . . . . . . . . . . . . . . . . . . . . . . . 269 15-13 flag clearing sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 15-14 sci status register 2 (s cs2) . . . . . . . . . . . . . . . . . . . . . . . . 273 15-15 sci data register (scdr) . . . . . . . . . . . . . . . . . . . . . . . . . . .274 15-16 sci baud rate register (scbr) . . . . . . . . . . . . . . . . . . . . . . 275
list of figures mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor list of figures 25 figure title page 16-1 spi i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . .281 16-2 spi module block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .282 16-3 full-duplex master-sla ve connections . . . . . . . . . . . . . . . . . 283 16-4 transmission format (cpha = 0) . . . . . . . . . . . . . . . . . . . . . 287 16-5 cpha/ss timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 16-6 transmission format (cpha = 1) . . . . . . . . . . . . . . . . . . . . . 288 16-7 transmission start delay (master) . . . . . . . . . . . . . . . . . . . . . 290 16-8 sprf/spte cpu interrupt timing . . . . . . . . . . . . . . . . . . . . . 291 16-9 missed read of overflow condition . . . . . . . . . . . . . . . . . . . .293 16-10 clearing sprf w hen ovrf interrupt is not enabled . . . . . . 294 16-11 spi interrupt request g eneration . . . . . . . . . . . . . . . . . . . . . 297 16-12 cpha/ss timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 16-13 spi control regist er (spcr) . . . . . . . . . . . . . . . . . . . . . . . . . 304 16-14 spi status and control register (s pscr) . . . . . . . . . . . . . . . 306 16-15 spi data register (spdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 17-1 i/o port register summary. . . . . . . . . . . . . . . . . . . . . . . . . . .312 17-2 port a data register (pta ) . . . . . . . . . . . . . . . . . . . . . . . . . . 316 17-3 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . . . 316 17-4 port a i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 17-5 port b data register (ptb ) . . . . . . . . . . . . . . . . . . . . . . . . . . 318 17-6 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . . . 319 17-7 port b i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 17-8 port c data register (ptc ) . . . . . . . . . . . . . . . . . . . . . . . . . . 320 17-9 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . . . 321 17-10 port c i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 17-11 port d data register (ptd ) . . . . . . . . . . . . . . . . . . . . . . . . . . 323 17-12 data direction register d (ddrd) . . . . . . . . . . . . . . . . . . . . . 324 17-13 port d i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 17-14 port d input pullup e nable register (ptdpue) . . . . . . . . . . . 325 17-15 port e data register (pte ) . . . . . . . . . . . . . . . . . . . . . . . . . . 326 17-16 data direction register e (ddre) . . . . . . . . . . . . . . . . . . . . . 328 17-17 port e i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 17-18 port f data register (ptf ). . . . . . . . . . . . . . . . . . . . . . . . . . .329 17-19 data direction register f (ddrf) . . . . . . . . . . . . . . . . . . . . . 330 17-20 port f i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331
list of figures technical data mc68hc908ab32 ? rev. 1.1 26 list of figures freescale semiconductor figure title page 17-21 port f input pullup enable register (ptfpue) . . . . . . . . . . . 332 17-22 port g data register (ptg ) . . . . . . . . . . . . . . . . . . . . . . . . . . 333 17-23 data direction register g (ddrg). . . . . . . . . . . . . . . . . . . . . 333 17-24 port g i/o circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 17-25 port h data register (pth ) . . . . . . . . . . . . . . . . . . . . . . . . . . 335 17-26 data direction register h (ddrh) . . . . . . . . . . . . . . . . . . . . . 336 17-27 port h i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 18-1 irq module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 341 18-2 irq i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . .341 18-3 irq status and control register (iscr) . . . . . . . . . . . . . . . . 343 19-1 kbi i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . .346 19-2 keyboard interrupt block diagram . . . . . . . . . . . . . . . . . . . . . 347 19-3 keyboard status and control register (kbscr) . . . . . . . . . . 350 19-4 keyboard interrupt enable register (kbier) . . . . . . . . . . . . . 351 20-1 cop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 20-2 configuration register 1 (config1) . . . . . . . . . . . . . . . . . . . 356 20-3 cop control register (copctl) . . . . . . . . . . . . . . . . . . . . . . 357 21-1 lvi module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .360 21-2 lvi i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 21-3 lvi status register (lvisr) . . . . . . . . . . . . . . . . . . . . . . . . . . 362 22-1 break module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 367 22-2 break module i/o register summary . . . . . . . . . . . . . . . . . . . 367 22-3 break status and control register (brkscr). . . . . . . . . . . . 369 22-4 break address register high (brkh) . . . . . . . . . . . . . . . . . . 370 22-5 break address register low (brkl) . . . . . . . . . . . . . . . . . . . 370 22-6 sim break status regist er (sbsr) . . . . . . . . . . . . . . . . . . . . 371 22-7 sim break flag control register (s bfcr) . . . . . . . . . . . . . . 372 23-1 spi master timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 23-2 spi slave timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 24-1 64-pin plastic quad flat pack (qfp) . . . . . . . . . . . . . . . . . . . 388
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor list of tables 27 technical data ? mc68hc908ab32 list of tables table title page 1-1 i/o pins summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 1-2 signal name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1-3 clock source summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2-1 vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 5-1 eeprom array address blo cks. . . . . . . . . . . . . . . . . . . . . . . . 73 5-2 eeprom program/erase mode select . . . . . . . . . . . . . . . . . . 78 7-1 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7-2 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 8-1 signal naming conventions. . . . . . . . . . . . . . . . . . . . . . . . . . .111 8-2 pin bit set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8-3 vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 8-4 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9-1 vco frequency multiplier (n) selectio n. . . . . . . . . . . . . . . . . 149 10-1 monitor mode entry conditi ons . . . . . . . . . . . . . . . . . . . . . . .160 10-2 mode differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 10-3 read (read memory) command . . . . . . . . . . . . . . . . . . . . . 163 10-4 write (write memory) command. . . . . . . . . . . . . . . . . . . . . 164 10-5 iread (indexed read) co mmand . . . . . . . . . . . . . . . . . . . . . 164 10-6 iwrite (indexed write) command . . . . . . . . . . . . . . . . . . . . 165 10-7 readsp (read stack po inter) command . . . . . . . . . . . . . . . 165 10-8 run (run user program) command . . . . . . . . . . . . . . . . . . . 166 10-9 monitor baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . 166 11-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11-2 prescaler selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 11-3 mode, edge, and level selection . . . . . . . . . . . . . . . . . . . . . . 191
list of tables technical data mc68hc908ab32 ? rev. 1.1 28 list of tables freescale semiconductor table title page 12-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 12-2 prescaler selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 12-3 mode, edge, and level selection . . . . . . . . . . . . . . . . . . . . . . 217 13-1 pit prescaler selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 14-1 mux channel select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 14-2 adc clock divide ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 15-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 15-2 start bit verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 15-3 data bit recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253 15-4 stop bit recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 15-5 character format selection . . . . . . . . . . . . . . . . . . . . . . . . . . 264 15-6 sci baud rate prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 15-7 sci baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 15-8 sci baud rate selection examples . . . . . . . . . . . . . . . . . . . .277 16-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 16-2 spi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 16-3 spi configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 16-4 spi master baud rate selection . . . . . . . . . . . . . . . . . . . . . . 308 17-1 port control register bits summary. . . . . . . . . . . . . . . . . . . .314 17-2 port a pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 17-3 port b pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 17-4 port c pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 17-5 port d pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 17-6 port e pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 17-7 port f pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 17-8 port g pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 17-9 port h pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 19-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 21-1 lviout bit indicati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 25-1 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor general description 29 technical data ? mc68hc908ab32 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 1.6.1 power supply pins (v dd and v ss ) . . . . . . . . . . . . . . . . . . . . 34 1.6.2 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . 35 1.6.3 external reset pin (rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6.4 external interrupt pin (irq ) . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6.5 analog power supply pin (v dda ) . . . . . . . . . . . . . . . . . . . . .35 1.6.6 analog ground pin (v ssa ) . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6.7 analog ground pin (a vss /v refl ). . . . . . . . . . . . . . . . . . . . .35 1.6.8 adc voltage reference pin (v refh ) . . . . . . . . . . . . . . . . . . 36 1.6.9 analog supply pin (v ddaref ) . . . . . . . . . . . . . . . . . . . . . . . 36 1.6.10 external filter capac itor pin (cgmxfc) . . . . . . . . . . . . . . . 36 1.6.11 port a input/output (i/o) pins (pta7?pta0) . . . . . . . . . . . . 36 1.6.12 port b i/o pins (ptb7/atd7?ptb 0/atd0) . . . . . . . . . . . . . 36 1.6.13 port c i/o pins (ptc5?p tc0) . . . . . . . . . . . . . . . . . . . . . . . 36 1.6.14 port d i/o pins (ptd7?p td0) . . . . . . . . . . . . . . . . . . . . . . . 37 1.6.15 port e i/o pins (pte7/spsck?pte0 /txd) . . . . . . . . . . . . . 37 1.6.16 port f i/o pins (ptf 7?ptf0/tach2) . . . . . . . . . . . . . . . . . 37 1.6.17 port g i/o pins (ptg2/kbd2?ptg 0/kbd0) . . . . . . . . . . . . 37 1.6.18 port h i/o pins (pth1/kbd4?pth0/ kbd3). . . . . . . . . . . . . 37 1.7 i/o pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 1.8 signal name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 1.9 clock source summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
general description technical data mc68hc908ab32 ? rev. 1.1 30 general description freescale semiconductor 1.2 introduction the mc68hc908ab32 is a me mber of the low-co st, high-performance m68hc08 family of 8-bi t microcontroller units (mcus) with embedded eeprom for user data st orage. all mcus in the family use the enhanced m68hc08 central processor unit (cpu08) and are available with a variety of modules, memory sizes and types, and package types. 1.3 features features of the mc68hc908a b32 include the following: high-performance m68hc08 architecture fully upward-compatible objec t code with m6805, m146805, and m68hc05 families memory map and pin functions compatible with mc68hc08ab32 and mc68hc08ab16 8-mhz internal bus frequency 32k-bytes user program flash memory with security 1 feature 512 bytes of on-chip eepro m with security feature 1k-byte of on-chip ram clock generator module (cgm) two 16-bit, 4-channel timer inte rface modules (tima and timb) with selectable input captur e, output compare, and pwm capability on each channel programmable interrupt timer (pit) serial peripheral in terface module (spi) serial communications interface module (sci) 8-channel. 8-bit analog-to-d igital converter (adc) low-power design (fully static with stop and wait modes) master reset pin and power-on reset 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the flash difficult for unauthorized users.
general description mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor general description 31 51 general-purpose inpu t/output (i/o) pins: ? 30 shared-function i/o pins ? 5-bit keyboard wakeup port ? selectable pullups on input s on port d and port f system protection features ? optional computer operati ng properly (cop) reset ? low-voltage detection with optional reset ? illegal opcode detecti on with optional reset ? illegal address detecti on with optional reset 64-pin quad flat pack (qfp) features of the cpu08 include the following: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index regist er and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications efficient c language support 1.4 mcu block diagram figure 1-1 shows the structure of the mc68hc908ab32.
general description technical data mc68hc908ab32 ? rev. 1.1 32 general description freescale semiconductor figure 1-1. mc68hc9 08ab32 block diagram clock generator module system integration module serial peripheral 4-channel timer interface module b low-voltage inhibit module keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 80 bytes user flash ? 32,256 bytes user ram ? 1024 bytes monitor rom ? 307 bytes user flash vectors ? 48 bytes single external irq module porta ddra ddre porte internal bus osc1 osc2 cgmxfc * rst * irq interface module interrupt module computer operating properly module pta7 ? pta0 v refh pte7/spsck pte6/mosi pte5/miso pte4/ss pte3/tach1 pte2/tach0 pte1/rxd pte0/txd a vss /v refl 4-channel timer interface module a 4.9125-mhz oscillator phase-locked loop serial communications interface module power-on reset module power v ss v dd v ssa v dda ? ports are software configurable with pullup device if input port. ? higher current drive port pins * pin contains int egrated pullup device ** pullup enabled when configur ed as keyboard interrupt pin v ddaref 8-bit analog-to-digital converter module user eeprom ? 512 bytes programmable interrupt timer module portb ddrb ptb7/atd7 ? ptb0/atd0 portc ddrc ptc5 ? ptc0 portd ddrd ptd7 ? ptd0 ?? ddrf portf ptf7 ? ptf6 ? ptf5/tbch1 ? ptf4/tbch0 ? ptf3/tbch3 ? ptf2/tbch2 ? ptf1/tach3 ? ptf0/tach2 ? portg ddrg ptg2/kbd2 ? ptg0/kbd0 ** porth ddrh pth1/kbd4 ? pth0/kbd3 ** (ptc2/mclk) (ptd6/taclk) (ptd4/tbclk)
general description mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor general description 33 1.5 pin assignments figure 1-2 shows the pin assignment for the mc68hc908ab32. figure 1-2. 64-pin qfp pin assignment ptf7 ptf4/tbch0 cgmxfc ptb7/atd7 ptf3/tbch3 ptf2/tbch2 ptf1/tach3 ptf0/tach2 rst irq ptc4 nc ptf5/tbch1 ptf6 pte0/txd pte1/rxd pte2/tach0 pte3/tach1 pth0/kbd3 ptd3 ptd2 a vss /vrefl v ddaref ptd1 ptd0 ptb6/atd6 ptb5/atd5 ptb4/atd4 ptb3/atd3 ptb2/atd2 ptb1/atd1 ptb0/atd0 pta7 v ssa v dda vrefh ptd7 ptd6/taclk ptd5 ptd4/tbclk pth1/kbd4 ptc5 ptc3 ptc2/mclk ptc1 ptc0 osc1 osc2 pte6/mosi pte4/ss pte5/miso pte7/spsck v ss v dd ptg0/kbd0 ptg1/kbd1 ptg2/kbd2 pta0 pta1 pta2 pta3 pta4 pta5 pta6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
general description technical data mc68hc908ab32 ? rev. 1.1 34 general description freescale semiconductor 1.6 pin functions description of pin func tions are provided here. 1.6.1 power supply pins (v dd and v ss ) v dd and v ss are the power s upply and ground pins . the mcu operates from a single power supply. fast signal transitions on mcu pins place high, short-duration current demands on the power supply. to preven t noise problems, take special care to provide power suppl y bypassing at the mcu as figure 1-3 shows. place the c1 bypass capacitor as close to the mcu as possible. use a high-frequency-response cerami c capacitor for c1. c2 is an optional bulk current bypa ss capacitor for use in appl ications that require the port pins to sour ce high current levels. figure 1-3. power supply bypassing v ss is also the ground for the port out put buffers and t he ground return for the serial clock in the serial peripheral inte rface module (spi). see section 16. serial peripher al interface module (spi) . v ss must be grounded for proper mcu operation. mcu v dd c2 c1 0.1 f v ss v dd + note: component values shown represent typical applications.
general description mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor general description 35 1.6.2 oscillator pins (osc1 and osc2) the osc1 and osc2 pins ar e the connections for the on-chip oscillator circuit. see section 9. clock generator module (cgm) . 1.6.3 external reset pin (rst ) a logic 0 on the rst pin forces the mcu to a known start-up state. rst is bidirectional, allowing a reset of t he entire system. it is driven low when any internal reset source is asserted. this pin contains an internal pullup resistor. see section 8. system in tegration module (sim) . 1.6.4 external interrupt pin (irq ) irq is an asynchronous external inte rrupt pin. this pin contains an internal pullup resistor. see section 18. external interrupt (irq) . 1.6.5 analog power supply pin (v dda ) v dda is the power supply pin for t he clock generator module (cgm). 1.6.6 analog ground pin (v ssa ) the v ssa analog ground pin is used only for the ground connections for the clock generator module (cgm) se ction of the circuit and should be decoupled as per the v ss digital ground pin. see section 9. clock generator module (cgm) . 1.6.7 analog ground pin (a vss /vrefl) the a vss analog ground pin is used only for the ground connections for the analog to digi tal convertor (adc) and shoul d be decoupled as per the v ss digital ground pin.
general description technical data mc68hc908ab32 ? rev. 1.1 36 general description freescale semiconductor 1.6.8 adc voltage reference pin (vrefh) vrefh is the power supply for sett ing the reference voltage vrefh. connect this pin to a volt age such that 1.5v < vrefh v ddaref . 1.6.9 analog supply pin (v ddaref ) the v ddaref analog supply pin is used on ly for the supply connections for the analog-to-digital convertor (adc). 1.6.10 external filter capacitor pin (cgmxfc) cgmxfc is an external filter capacito r connection for the cgm. see section 9. clock gene rator module (cgm) . 1.6.11 port a input/output (i/o) pins (pta7 ? pta0) pta7?pta0 are general-purpose bidi rectional i/o port pins. see section 17. input/output (i/o) ports . 1.6.12 port b i/o pins (ptb7/atd7?ptb0/atd0) ptb7?ptb0 are special function, bidirectional port pins. ptb7?ptb0 are shared with the a nalog to digital conve rtor (adc) input pins atd7?atd0. see section 14. anal og-to-digital converter (adc) and section 17. input/output (i/o) ports . 1.6.13 port c i/o pins (ptc5?ptc0) ptc5?ptc0 are general-purpose bidirect ional i/o port pins. ptc2 is a special function port pin that is s hared with the system clock output pin, mclk. see section 17. input/ou tput (i/o) ports .
general description mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor general description 37 1.6.14 port d i/o pins (ptd7?ptd0) ptd7?ptd0 are gener al-purpose bidire ctional i/o port pins. ptd6 and ptd4 are special function port pins that are shared with the timer interface modules (tima and timb). see section 11. ti mer interface module a (tima) and section 12. timer in terface module b (timb) . 1.6.15 port e i/o pins (pte7/spsck?pte0/txd) pte7?pte0 are special function, bidirectional port pins. pte7?pte4 are shared with the serial peripheral interface mode (s pi), pte3?pte2 are shared with timer a (tima), a nd pte1?pte0 are sh ared with the serial communications interface (sci). see section 15. serial communications interface module (sci) , section 16. serial peripheral interf ace module (spi) , section 11. timer interface module a (tima) , and section 17. input/o utput (i/o) ports . 1.6.16 port f i/o pins (ptf7?ptf0/tach2) ptf7?ptf6 are general -purpose bidirecti onal i/o port pins. ptf5?ptf0 are special function, bi directional port pins. ptf5?ptf2 are shared with timer b (timb), and ptf 1?ptf0 are shared with timer a (tima). see section 11. timer inte rface module a (tima) , section 12. timer interf ace module b (timb) , and section 17. input/output (i/o) ports . 1.6.17 port g i/o pins (ptg2/kbd2?ptg0/kbd0) ptg2?ptg0 are general-purpose bidi rectional i/o pins with keyboard wakeup function. see section 19. keyboard in terrupt module (kbi) and section 17. input/output (i/o) ports . 1.6.18 port h i/o pins (pth1/kbd4?pth0/kbd3) pth1?pth0 are general-purpose bidire ctional i/o pins with keyboard wakeup function. see section 19. keyboard in terrupt module (kbi) and section 17. input/output (i/o) ports .
general description technical data mc68hc908ab32 ? rev. 1.1 38 general description freescale semiconductor 1.7 i/o pin summary table 1-1. i/o pins summary pin name function driver type hysteresis reset state pta7?pta0 general purpose i/o dual state no input (hi-z) ptb7/atd7?ptb0/atd0 general purpose i/o / adc channel dual state no input (hi-z) ptc5?ptc3 general purpose i/o dual state no input (hi-z) ptc2/mclk general purpose i/o / system clock dual state no input (hi-z) ptc1?ptc0 general purpose i/o dual state no input (hi-z) ptd7 general purpose i/o dual state no input (hi-z) ptd6/taclk general purpose i/o / timer external input clock dual state no input (hi-z) ptd5 general purpose i/o dual state no input (hi-z) ptd4/tbclk general purpose i/o / timer external input clock dual state no input (hi-z) ptd3?ptd0 general purpose i/o dual state no input (hi-z) pte7/spsck general purpose i/o / spi clock dual state (open drain) yes input (hi-z) pte6/mosi general purpose i/o / spi data path dual state (open drain) yes input (hi-z) pte5/miso general purpose i/o / spi data path dual state (open drain) yes input (hi-z) pte4/ss general purpose i/o / spi slave select dual state yes input (hi-z) pte3/tach1 general purpose i/o / timer a channel 1 dual state yes input (hi-z) pte2/tach0 general purpose i/o / timer a channel 0 dual state yes input (hi-z) pte1/rxd general purpose i/o / sci receive data dual state yes input (hi-z) pte0/txd general purpose i/o / sci transmit data dual state yes input (hi-z) ptf7?ptf6 general purpose i/o dual state yes input (hi-z) ptf5/tbch1 general purpose i/o / timer b channel 1 dual state yes input (hi-z)
general description mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor general description 39 details of the clock connections to each of the modules on the mc68hc908ab32 are shown in table 1-2 . a short description of each clock source is also given in table 1-3 . ptf4/tbch0 general purpose i/o / timer b channel 0 dual state yes input (hi-z) ptf3/tbch3 general purpose i/o / timer b channel 3 dual state yes input (hi-z) ptf2/tbch2 general purpose i/o / timer b channel 2 dual state yes input (hi-z) ptf1/tach3 general purpose i/o / timer a channel 3 dual state yes input (hi-z) ptf0/tach2 general purpose i/o / timer a channel 2 dual state yes input (hi-z) ptg2/kbd2?ptg0/kbd0 general purpose i/o with key wakeup feature dual state yes input (hi-z) pth1/kbd4?pth0/kbd3 general purpose i/o with key wakeup feature dual state yes input (hi-z) v dd logical chip power supply na na na v ss logical chip ground na na na v dda analog power supply (cgm) na na na v ssa analog ground (cgm) na na na v refh adc reference voltage na na na a vss /v refl adc ground and reference voltage na na na v ddaref adc power supply na na na osc1 external clock in na na input (hi-z) osc2 external clock out na na output cgmxfc pll loop filter cap na na na irq external interrupt request na na input (pullup) rst reset na na input (pullup) table 1-1. i/o pins summary pin name function driver type hysteresis reset state
general description technical data mc68hc908ab32 ? rev. 1.1 40 general description freescale semiconductor 1.8 signal name conventions 1.9 clock source summary table 1-2. signal name conventions signal name description cgmxclk buffered version of osc1 from clock generator module (cgm) cgmout pll-based or osc1-based clock output from cgm module) bus clock cgmout divided by two spsck spi serial clock (see 16.13.3 spsck (serial clock) ) tac l k external clock input for tima (see 11.9.1 tima clock pin ) tbclk external clock input for timb (see 12.9.1 timb clock pin ) table 1-3. clock source summary module clock source adc cgmxclk or bus clock cop cgmxclk cpu bus clock eeprom cgmxclk or bus clock rom bus clock ram bus clock spi spsck sci cgmxclk tima bus clock or ptd6/taclk timb bus clock or ptd4/tbclk pit bus clock kbi bus clock
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor memory map 41 technical data ? mc68hc908ab32 section 2. memory map 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.3 unimplemented memory loc ations . . . . . . . . . . . . . . . . . . . . . 41 2.4 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.5 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.2 introduction the cpu08 can address 64k-bytes of memory space. the memory map, shown in figure 2-1 , includes: 32, 256 bytes of user flash memory 512 bytes of eeprom 1024 bytes of random-access memory (ram) 48 bytes of user-defined vectors 307 bytes of monitor rom 2.3 unimplemented memory locations accessing an unimplemented locati on can cause an illegal address reset if illegal address resets are enabled. in the memory map ( figure 2-1 ) and in register figures in this document, unimplemented locations are shaded.
memory map technical data mc68hc908ab32 ? rev. 1.1 42 memory map freescale semiconductor 2.4 reserved me mory locations accessing a reserved location can hav e unpredictable effects on mcu operation. in the figure 2-1 and in register figures in this document, reserved locations are marked with the word reserv ed or with the letter r. 2.5 input/output (i/o) section most of the control, status, and data register s are in the zero page $0000?$004f. additional i/o register s have the following addresses: $fe00; sim break st atus register, sbsr $fe01; sim reset st atus register, srsr $fe03; sim break flag control register, sbfcr $fe08; flash contro l register, flcr $fe0c; break address register high, brkh $fe0d; break address register low, brkl $fe0e; break status and control register, brkscr $fe0f; lvi status register, lvisr $fe10; eeprom divider non-volatile regist er high, eedivhnvr $fe11; eeprom divider non-volatile regist er low, eedivlnvr $fe1a; eeprom timebase divi der register high, eedivh $fe1b; eeprom timebase divi der register low, eedivl $fe1c; eeprom non-volati le register, eenvr $fe1d; eeprom cont rol register, eecr $fe1f; eeprom array confi guration register, eeacr $ff7e; flash block prot ect register, flbpr $ffff; cop control register, copctl data registers are shown in figure 2-2 , table 2-1 is a list of vector locations.
memory map mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor memory map 43 $0000 i/o registers 80 bytes $004f $0050 ram 1,024 bytes $044f $0450 unimplemented 176 bytes $04ff $0500 reserved 128 bytes $057f $0580 unimplemented 640 bytes $07ff $0800 eeprom 512 bytes $09ff $0a00 unimplemented 30,208 bytes $7fff $8000 flash memory 32,256 bytes $fdff $fe00 sim break status register (sbsr) $fe01 sim reset status register (srsr) $fe02 reserved $fe03 sim break flag control register (sbfcr) $fe04 $fe07 reserved 4 bytes $fe08 flash control register (flcr) figure 2-1. memory map
memory map technical data mc68hc908ab32 ? rev. 1.1 44 memory map freescale semiconductor $fe09 $fe0b reserved 3 bytes $fe0c break address register high (brkh) $fe0d break address register low (brkl) $fe0e break status and control register (brkscr) $fe0f lvi status register (lvisr) $fe10 eeprom divider non-volatile register high (eedivhnvr) $fe11 eeprom divider non-volati le register low (eedivlnvr) $fe12 $fe19 reserved 8 bytes $fe1a eeprom timebase divide r register high (eedivh) $fe1b eeprom timebase divider register low (eedivl) $fe1c eeprom non-volatile register (eenvr) $fe1d eeprom control register (eecr) $fe1e reserved $fe1f eeprom array confi guration register (eeacr) $fe20 monitor rom 307 bytes $ff52 $ff53 unimplemented 43 bytes $ff7d $ff7e flash block protect register (flbpr) $ff7f unimplemented 65 bytes $ffbf $ffc0 reserved flash memory 16 bytes reserved for compatibility with hc08ab16/24/32 $ffcf $ffd0 flash vectors 48 bytes $ffff figure 2-1. memory map (continued)
memory map mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor memory map 45 addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) read: 0 0 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) read: mclken 0 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 port e data register (pte) read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0009 port f data register (ptf) read: ptf7 ptf6 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 write: reset: unaffected by reset = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 1 of 11)
memory map technical data mc68hc908ab32 ? rev. 1.1 46 memory map freescale semiconductor $000a port g data register (ptg) read: 00000 ptg2 ptg1 ptg0 write: reset: unaffected by reset $000b port h data register (pth) read: 000000 pth1 pth0 write: reset: unaffected by reset $000c data direction register e (ddre) read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 $000d data direction register f (ddrf) read: ddrf7 ddrf6 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: reset:00000000 $000e data direction register g (ddrg) read: 00000 ddrg2 ddrg1 ddrg0 write: reset:00000000 $000f data direction register h (ddrh) read: 000000 ddrh1 ddrh0 write: reset:00000000 $0010 spi control register (spcr) read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 $0011 spi status and control register (spscr) read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 $0012 spi data register (spdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0013 sci control register 1 (scc1) read: loops ensci txinv m wake ilty pen pty write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 2 of 11)
memory map mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor memory map 47 $0014 sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $0015 sci control register 3 (scc3) read: r8 t8 r r orie neie feie peie write: reset: unaffected unaffected 000000 $0016 sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: reset:11000000 $0017 sci status register 2 (scs2) read: 000000bkfrpf write: reset:00000000 $0018 sci data register (scdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 sci baud rate register (scbr) read: 0 0 scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 $001a irq status and control register (iscr) read: 0000irqf0 imask mode write: ack reset:00000000 $001b keyboard status and control register (kbscr) read: 0000 keyf 0 imaskk modek write: ackk reset:00000000 $001c pll control register (pctl) read: pllie pllf pllon bcs 1111 write: reset:00101111 $001d pll bandwidth control register (pbwc) read: auto lock acq xld 0000 write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 3 of 11)
memory map technical data mc68hc908ab32 ? rev. 1.1 48 memory map freescale semiconductor $001e pll programming register (ppg) read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset:01100110 $001f configuration register 1 (config1) ? read: lvistop r lvirstd lvipwrd ssrec coprs stop copd write: reset:00000000 ? one-time writable register after each reset. $0020 timer a status and control register (tasc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0021 keyboard interrupt enable register (kbier) read: 0 0 0 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 $0022 timer a counter register high (tacnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0023 timer a counter register low (tacntl) read: bit 7 654321bit 0 write: reset:00000000 $0024 timer a counter modulo register high (tamodh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $0025 timer a counter modulo register low (tamodl) read: bit 7654321bit 0 write: reset:11111111 $0026 timer a channel 0 status and control register (tasc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0027 timer a channel 0 register high (tach0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 4 of 11)
memory map mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor memory map 49 $0028 timer a channel 0 register low (tach0l) read: bit 7654321bit 0 write: reset: indeterminate after reset $0029 timer a channel 1 status and control register (tasc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $002a timer a channel 1 register high (tach1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002b timer a channel 1 register low (tach1l) read: bit 7654321bit 0 write: reset: indeterminate after reset $002c timer a channel 2 status and control register (tasc2) read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset:00000000 $002d timer a channel 2 register high (tach2h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002e timer a channel 2 register low (tach2l) read: bit 7654321bit 0 write: reset: indeterminate after reset $002f timer a channel 3 status and control register (tasc3) read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset:00000000 $0030 timer a channel 3 register high (tach3h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0031 timer a channel 3 register low (tach3l) read: bit 7654321bit 0 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 5 of 11)
memory map technical data mc68hc908ab32 ? rev. 1.1 50 memory map freescale semiconductor $0032 timer b channel 2 status and control register (tbsc2) read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset:00000000 $0033 timer b channel 2 register high (tbch2h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0034 timer b channel 2 register low (tbch2l) read: bit 7654321bit 0 write: reset: indeterminate after reset $0035 timer b channel 3 status and control register (tbsc3) read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset:00000000 $0036 timer b channel 3 register high (tach3h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0037 timer b channel 3 register low (tbch3l) read: bit 7654321bit 0 write: reset: indeterminate after reset $0038 analog-to-digital status and control register (adscr) read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 $0039 analog-to-digital data register (adr) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset:00000000 $003a analog-to-digital clock register (adclk) read: adiv2 adiv1 adiv0 adiclk 0000 write: reset:00000000 $003b reserved read: rrrrrrrr write: reset: addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 6 of 11)
memory map mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor memory map 51 $003c reserved read: rrrrrrrr write: reset: $003d port d input pullup enable register (ptdpue) read: ptdpue7 ptdpue6 ptdpue5 ptdpue4 ptdpue3 ptdpue2 ptdpue1 ptdpue0 write: reset:00000000 $003e port f input pullup enable register (ptfpue) read: ptfpue7 ptfpue6 ptfpue5 ptfpue4 ptfpue3 ptfpue2 ptfpue1 ptfpue0 write: reset:00000000 $003f configuration register 2 (config2) ? read: r eedivclk rrrrrr write: reset: 0 ? one-time writable register after each reset. $0040 timer b status and control register (tbsc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0041 timer b counter register high (tbcnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0042 timer b counter register low (tbcntl) read: bit 7 654321bit 0 write: reset:00000000 $0043 timer b counter modulo register high (tbmodh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $0044 timer b counter modulo register low (tbmodl) read: bit 7654321bit 0 write: reset:11111111 $0045 timer b channel 0 status and control register (tbsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 7 of 11)
memory map technical data mc68hc908ab32 ? rev. 1.1 52 memory map freescale semiconductor $0046 timer b channel 0 register high (tbch0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0047 timer b channel 0 register low (tbch0l) read: bit 7654321bit 0 write: reset: indeterminate after reset $0048 timer b channel 1 status and control register (tbsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0049 timer b channel 1 register high (tbch1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $004a timer b channel 1 register low (tbch1l) read: bit 7654321bit 0 write: reset: indeterminate after reset $004b pit status and control register (psc) read: pof poie pstop 00 pps2 pps1 pps0 write: 0 prst reset:00100000 $004c pit counter register high (pcnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $004d pit counter register low (pcntl) read: bit 7 654321bit 0 write: reset:00000000 $004e pit counter modulo register high (pmodh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $004f pit counter modulo register low (pmodl) read: bit 7654321bit 0 write: reset:11111111 addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 8 of 11)
memory map mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor memory map 53 $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset:00000000 note: writing a l ogic 0 clears sbsw. $fe01 sim reset status register (srsr) read: por pin cop ilop ilad 0 lvi 0 write: por:10000000 $fe02 reserved read: rrrrrrrr write: reset:00000000 $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe04 reserved read: rrrrrrrr write: reset: $fe05 reserved read: rrrrrrrr write: reset: $fe06 reserved read: rrrrrrrr write: reset: $fe07 reserved read: rrrrrrrr write: reset: $fe08 flash control register (flcr) read: 0000 hven mass erase pgm write: reset:00000000 $fe09 reserved read: rrrrrrrr write: reset: addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data registers (sheet 9 of 11)
memory map technical data mc68hc908ab32 ? rev. 1.1 54 memory map freescale semiconductor $fe0a reserved read: rrrrrrrr write: reset: $fe0b reserved read: rrrrrrrr write: reset: $fe0c break address register high (brkh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0d break address register low (brkl) read: bit 7654321bit 0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 $fe0f low-voltage inhibit status register (lvisr) read: lviout 0000000 write: reset:00000000 $fe10 eediv non-volatile register high (eedivhnvr)* read: eedivsecd rrrreediv10eediv9eediv8 write: reset: unaffected by reset; $ff when blank $fe11 eediv non-volatile register low (eedivlnvr)* read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: unaffected by reset; $ff when blank * non-volatile flash regi ster; write by programming. $fe1a ee divider register high (eedivh) read: eedivsecd rrrreediv10eediv9eediv8 write: reset: contents of eedivhnvr ($fe10) $fe1b ee divider register low (eedivl) read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: contents of eedivlnvr ($fe11) addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data regi sters (sheet 10 of 11)
memory map mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor memory map 55 $fe1c eeprom non-volatile register (eenvr)* read: con3 con2 con1 eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: unaffected by reset; $ff when blank $fe1d eeprom control register (eecr) read: eedum 0 eeoff eeras1 eeras0 eelat auto eepgm write: reset:00000000 $fe1e reserved read: rrrrrrrr write: reset: $fe1f eeprom array configuration register (eeacr) read: con3 con2 con1 eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: contents of eenvr ($fe1c) $ff7e flash block protect register (flbpr)* read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset: unaffected by reset * non-volatile flash regi ster; write by programming. $ffff cop control register (copctl) read: low byte of reset vector write: writing clears co p counter (any value) reset: unaffected by reset addr.register name bit 7654321bit 0 = unimplemented r = reserved figure 2-2. control, status, and data regi sters (sheet 11 of 11)
memory map technical data mc68hc908ab32 ? rev. 1.1 56 memory map freescale semiconductor table 2-1. vector addresses vector priority address vector lowest $ffd0 adc conversion complete vector (high) $ffd1 adc conversion complete vector (low) $ffd2 keyboard vector (high) $ffd3 keyboard vector (low) $ffd4 sci transmit vector (high) $ffd5 sci transmit vector (low) $ffd6 sci receive vector (high) $ffd7 sci receive vector (low) $ffd8 sci error vector (high) $ffd9 sci error vector (low) $ffda reserved $ffdb reserved $ffdc reserved $ffdd reserved $ffde timer b channel 3 vector (high) $ffdf timer b channel 3 vector (low) $ffe0 timer b channel 2 vector (high) $ffe1 timer b channel 2 vector (low) $ffe2 spi transmit vector (high) $ffe3 spi transmit vector (low) $ffe4 spi receive vector (high) $ffe5 spi receive vector (low) $ffe6 timer b overflow vector (high) $ffe7 timer b overflow vector (low) $ffe8 timer b channel 1 vector (high) $ffe9 timer b channel 1 vector (low) $ffea timer b channel 0 vector (high) $ffeb timer b channel 0 vector (low) $ffec timer a overflow vector (high) $ffed timer a overflow vector (low) $ffee timer a channel 3 vector (high) $ffef timer a channel 3 vector (low) $fff0 timer a channel 2 vector (high) $fff1 timer a channel 2 vector (low) $fff2 timer a channel 1 vector (high) $fff3 timer a channel 1 vector (low) $fff4 timer a channel 0 vector (high) $fff5 timer a channel 0 vector (low) $fff6 programmable interrupt timer (high) $fff7 programmable interrupt timer (low) $fff8 pll vector (high) $fff9 pll vector (low) $fffa irq vector (high) $fffb irq vector (low) $fffc swi vector (high) $fffd swi vector (low) highest $fffe reset vector (high) $ffff reset vector (low)
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor random-access memory (ram) 57 technical data ? mc68hc908ab32 section 3. random-access memory (ram) 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 3.2 introduction this section describes the 10 24 bytes of ram (random-access memory). 3.3 functional description addresses $0050 through $0 44f are ram locations. the location of the stack ram is programmable. the 16-bit stack pointer allows the stack to be anywhere in the 64k-byte memory space. note: for correct operation, the stack pointer must point only to ram locations. within page zero are 176 bytes of ra m. because the location of the stack ram is programmable, all page zero ram locations can be used for i/o control and user data or code. when the stack pointer is moved from its reset location at $00ff out of page zero, direct addressing mode instructions can efficiently acce ss all page zero ram locations. page zero ram, therefore, provides i deal locations for frequently accessed global variables. before processing an interrupt, the cp u uses five bytes of the stack to save the contents of the cpu registers. note: for m6805 compatibility, the h register is not stacked.
random-access memory (ram) technical data mc68hc908ab32 ? rev. 1.1 58 random-access memory (ram) freescale semiconductor during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack po inter decrements during pushes and increments during pulls. note: be careful when using nested subr outines. the cpu ma y overwrite data in the ram during a s ubroutine or during the interrupt stacking operation.
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor flash memory 59 technical data ? mc68hc908ab32 section 4. flash memory 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 4.4 flash control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.5 flash page erase operatio n . . . . . . . . . . . . . . . . . . . . . . . . . 61 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.7 flash program/read operation . . . . . . . . . . . . . . . . . . . . . . . 63 4.8 flash block protecti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 4.8.1 flash block protect regi ster . . . . . . . . . . . . . . . . . . . . . . . 66 4.9 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.10 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.2 introduction this section describes the operat ion of the embedd ed flash memory. this memory can be r ead, programmed, and er ased from a single external supply. the program and er ase operations are enabled through the use of an internal charge pump. 4.3 functional description the flash memory is an array of 32, 256 bytes with an additional 48 bytes of user vectors and one byte of block protection. an erased bit reads as logic 1 and a program med bit reads as a logic 0 . memory in the flash array is organized into two rows per page basi s. for the 32k word by 8-bit embedded flash memory , the page size is 128 bytes per
flash memory technical data mc68hc908ab32 ? rev. 1.1 60 flash memory freescale semiconductor page. hence the minimum erase page size is 128 bytes. program and erase operations are facilitated thro ugh control bits in the flash control register (flcr). details for thes e operations appear later in this section. the address ranges for the user me mory and vectors are: $8000?$fdff; user memory. $ff7e; flash block protect register. $fe08 ; flash control register. $ffdc?$ffff; these locations are reserved for user-defined interrupt and reset vectors. programming tools are available from freescale. contact your local freescale representative for more information. note: a security feature prevents vi ewing of the flash contents. 1 4.4 flash control register the flash control register (flcr) controls flash program and erase operations. hven ? high-volt age enable bit this read/write bit enables the charge pump to dr ive high voltages for program and erase operati ons in the array. hv en can only be set if either pgm = 1 or erase = 1 and the proper sequence for program or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the flash difficult for unauthorized users. address: $fe08 bit 7654321bit 0 read: 0000 hven mass erase pgm write: reset:00000000 figure 4-1. flash cont rol register (flcr)
flash memory mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor flash memory 61 mass ? mass erase control bit setting this read/write bit configur es the 32k-byte flash array for mass erase operation. 1 = mass erase oper ation selected 0 = mass erase oper ation unselected erase ? erase control bit this read/write bit conf igures the memory for erase operation. erase is interlocked wit h the pgm bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = erase operation selected 0 = erase operation unselected pgm ? program control bit this read/write bit conf igures the memory fo r program operation. pgm is interlocked with the erase bit such t hat both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation unselected 4.5 flash page erase operation use this step-by-st ep procedure to erase a page (128 bytes) of flash memory to read as logic 1: 1. set the erase bit, a nd clear the mass bit in the flash control register. 2. read the flash blo ck protect register. 3. write any data to any flash address within the page address range desired. 4. wait for a time, t nvs (min. 10 s) 5. set the hven bit. 6. wait for a time, t erase (min. 1ms) 7. clear the erase bit. 8. wait for a time, t nvh (min. 5 s)
flash memory technical data mc68hc908ab32 ? rev. 1.1 62 flash memory freescale semiconductor 9. clear the hven bit. 10. after a time, t rcv (typ. 1 s), the memory can be accessed again in read mode. note: while these operations mu st be performed in th e order shown, other unrelated operations may o ccur between the steps. 4.6 flash mass erase operation use this step-by-step procedure to er ase entire flash memory to read as logic 1: 1. set both the erase bit, and the ma ss bit in the flash control register. 2. read from the flash bl ock protect register. 3. write any data to any flash address* within the flash memory address range. 4. wait for a time, t nvs (min. 10 s) 5. set the hven bit. 6. wait for a time, t merase (min. 4ms) 7. clear the erase bit. 8. wait for a time, t nvhl (min. 100 s) 9. clear the hven bit. 10. after a time, t rcv (min. 1 s), the memory can be accessed again in read mode. * when in monitor mode, with security sequence failed (see 10.5 security ), write to the flash block protect register instead of any flash address. note: programming and erasing of flash locations c annot be performed by code being executed from the flash memory. while these operations must be performed in the order shown, other unrelated operations may occur between the steps.
flash memory mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor flash memory 63 4.7 flash program/read operation programming of the flash memory is done on a row basis. a row consists of 64 consecutive bytes starting from a ddresses $xx00, $xx40, $0080 and $ xxc0. use this step-by-step procedure to program a row of flash memory ( figure 4-2 is a flowchart representation): note: in order to avoid program disturbs , the row must be erased before any byte on that ro w is programmed. 1. set the pgm bit. this configur es the memory for program operation and enables the latchi ng of address and data for programming. 2. read from the flash bl ock protect register. 3. write any data to any flash address within t he row address range desired. 4. wait for a time, t nvs (min. 10 s). 5. set the hven bit. 6. wait for a time, t pgs (min. 5 s). 7. write data to the flash address to be programmed.* 8. wait for a time, t prog (min. 30 s). 9. repeat step 7 and 8 until all the bytes within the row are programmed. 10. clear the pgm bit.* 11. wait for a time, t nvh (min. 5 s). 12. clear the hven bit. 13. after time, t rcv (min. 1 s), the memory can be accessed in read mode again. * the time between each flash address change, or the time between the last flash address programmed to clearing pgm bit, must no t exceed the maximum programming time, t prog max. this program sequence is repeated th roughout the memory until all data is programmed.
flash memory technical data mc68hc908ab32 ? rev. 1.1 64 flash memory freescale semiconductor note: programming and erasing of flash locations c annot be performed by code being executed from the flash memory. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. do not exceed t prog maximum. see 23.13 flash memory characteristics . 4.8 flash block protection due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provision is made for protecting a block of memory from unintentional erase or program operations due to system malfunction. this protection is done by using of a flash block protect register (flbpr). the flbpr de termines the range of the flash memory which is to be protected. the r ange of the protected area starts from a location defined by flbpr and ends at the bottom of the flash memory ($ffff). when the memory is protected, the hven bit cannot be set in either erase or prog ram operations. note: in performing a program or erase op eration, the flash block protect register must be read after setting the pg m or erase bit and before asserting the hven bit when the flbpr is program with all 0? s, the entire memory is protected from being programmed and erased. when all the bits are erased (all 1?s), the entire memory is accessible for program and erase. when bits within the flbpr are pr ogrammed, they lock a block of memory, address range s as shown in 4.8.1 flash block protect register . once the flbpr is programmed with a value ot her than $ff, any erase or program of the flbpr or the pr otected block of flash memory is prohibited. the flbpr itself can be erased or programmed only with an exte rnal voltage, v tst , present on the irq pin. this voltage also allows entry from re set into the monitor mode.
flash memory mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor flash memory 65 figure 4-2. flash programming flowchart set hven bit read the flash block protect register write any data to any flash address within the row address range desired wait for a time, t nvs set pgm bit wait for a time, t pgs write data to the flash address to be programmed wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv completed programming this row? y n end of programming the time between each flash addres s change (step 7 to step 7), or must not exceed the maximum programming time, t prog max. the time between the last flash address programmed to clearing pgm bit (step 7 to step 10) note: 1 2 3 4 5 6 7 8 10 11 12 13 algorithm for programming a row (64 bytes) of flash memory this row program algorithm assumes the row/s to be programmed are initially erased.
flash memory technical data mc68hc908ab32 ? rev. 1.1 66 flash memory freescale semiconductor 4.8.1 flash block protect register the flash block protect register ( flbpr) is implemented as a byte within the flash memory, and ther efore can only be written during a programming sequence of the flash memo ry. the value in this register determines the starting location of the protected range within the flash memory. bpr[7:0] ? flash block protect bits these eight bits represent bits [ 14:7] of a 16-bit memory address. bit-15 is logic 1 and bits [6:0] are logic 0s. the resultant 16-bit address is used for specifying the start address of the flash memory for block pr otection. the flash is protected from this start address to the end of flash me mory, at $ffff. with this mechanism, the protect start address can be xx00 and xx80 (128 bytes page boundaries) wi thin the flash memory. figure 4-4. flash block protect start address address: $ff7e bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 bpr0 write: reset:uuuuuuuu u = unaffected by reset. initial value from factory is 1. write to this register is by a pr ogramming sequence to the flash memory. figure 4-3. flash block pr otect register (flbpr) 1 flbpr value 16-bit memory address 0000000 start address of flash block protect
flash memory mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor flash memory 67 examples of protect start address: 4.9 wait mode putting the mcu into wa it mode while the flash is in read mode does not affect the operation of the flash me mory directly, bu t there will not be any memory activity si nce the cpu is inactive. the wait instruction should not be executed while performing a program or erase operation on the flash, otherwise the operation will discontinue, and the flash will be on standby mode. 4.10 stop mode putting the mcu into stop mode whil e the flash is in read mode does not affect the operation of the flash me mory directly, bu t there will not be any memory activity si nce the cpu is inactive. the stop instruction should not be executed while performing a program or erase operation on the fla sh, otherwise t he operation will discontinue, and the flash will be on standby mode note: standby mode is the power saving mo de of the flash module in which all internal control signals to th e flash are inactive and the current consumption of the fl ash is at a minimum. bpr[7:0] start of address of protect range $00 the entire flash memory is protected. $01 ( 0000 0001 ) $8080 (1 000 0000 1 000 0000) $02 ( 0000 0010 ) $8100 (1 000 0001 0 000 0000) and so on... $fe ( 1111 1110 ) $ff00 (1 111 1111 0 000 0000) $ff the entire flash memory is not protected. note: the end address of the protected range is always $ffff.
flash memory technical data mc68hc908ab32 ? rev. 1.1 68 flash memory freescale semiconductor
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor eeprom 69 technical data ? mc68hc908ab32 section 5. eeprom 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 5.5 eeprom configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 5.6 eeprom timebase requirem ents . . . . . . . . . . . . . . . . . . . . . 72 5.7 eeprom security options. . . . . . . . . . . . . . . . . . . . . . . . . . . .72 5.8 eeprom block protec tion . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 5.9 eeprom programming and er asing . . . . . . . . . . . . . . . . . . . . 73 5.9.1 eeprom programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 5.9.2 eeprom erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5.10 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 5.10.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 5.10.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 5.11 eeprom registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.11.1 eeprom control register . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.11.2 eeprom array configur ation register . . . . . . . . . . . . . . . . 79 5.11.2.1 eeprom non-volatile register. . . . . . . . . . . . . . . . . . . . 80 5.11.3 eeprom timebase divider register . . . . . . . . . . . . . . . . . 80 5.11.3.1 eeprom timebase divider non-volatile register . . . . . 82 5.2 introduction this section describes the 512 bytes el ectrically erasable programmable read-only-memory (eeprom).
eeprom technical data mc68hc908ab32 ? rev. 1.1 70 eeprom freescale semiconductor 5.3 features features of the eeprom include the following: 512 bytes non-volatile memory byte, block or bulk erasable operations non-volatile eeprom configuration and block protection options on-chip charge pump fo r programming/erasing security option addr.register name bit 7654321bit 0 $fe10 eediv non-volatile register high (eedivhnvr)* read: eedivsecd rrrreediv10eediv9eediv8 write: reset: unaffected by reset; $ff when blank $fe11 eediv non-volatile register low (eedivlnvr)* read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: unaffected by reset; $ff when blank $fe1a ee divider register high (eedivh) read: eedivsecd rrrreediv10eediv9eediv8 write: reset: contents of eedivhnvr ($fe10) $fe1b ee divider register low (eedivl) read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: contents of eedivlnvr ($fe11) $fe1c eeprom non-volatile register (eenvr)* read: con3 con2 con1 eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: unaffected by reset; $ff when blank; factory programmed $10 $fe1d eeprom control register (eecr) read: eedum 0 eeoff eeras1 eeras0 eelat auto eepgm write: reset:00000000 figure 5-1. eeprom i /o register summary
eeprom mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor eeprom 71 5.4 functional description the 512 bytes of eeprom is lo cated at $0800?$09ff, and can be programmed or erased without an add itional external high voltage supply. the program and erase operations are enabled through the use of an internal charge pump. for eac h byte of eeprom , the write/erase endurance is 10,000 cycles. 5.5 eeprom configuration the 8-bit eeprom non-v olatile register (e envr) and the 16-bit eeprom timebase divider non-volati le register (e edivnvr) contain the default settings for the following ee prom configurations: security option block protection eeprom timebase reference eenvr and eedivnvr are non-volatile , eeprom regist ers. they are programmed and erased in the sa me way as eeprom bytes. the contents of these registers are loaded into th eir respective volatile registers during a mcu reset. the valu es in these read/ write, volatile registers define the e eprom configurations. for eenvr, the co rresponding volatile regist er is the eeprom array configuration re gister (eeacr). $fe1f eeprom array configuration register (eeacr) read: con3 con2 con1 eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: contents of eenvr ($fe1c) * non-volatile eeprom regi ster; write by programming. = unimplemented r = reserved figure 5-1. eeprom i /o register summary
eeprom technical data mc68hc908ab32 ? rev. 1.1 72 eeprom freescale semiconductor for the eedivnvr (two 8-bit registers: eedivhnvr and eedivlnvr), the corresponding volatile register is the e eprom timebase divider register (eediv: eedivh and eedivl)
eeprom mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor eeprom 73 5.6 eeprom timebase requirements a 35 s timebase is required by the ee prom control circ uit for program and erase of eeprom content. this timebase is derived from dividing the cgmxclk or bus clock (selec ted by eedivclk bit in config2 register) using a timebase divider circuit, controll ed by the 16-bit eeprom timebase divider r egister (eedivh and eedivl). as the cgmxclk or bus clock is us er selected, the eeprom timebase divider register must be configured with the appropr iate value to obtain the 35 s. the timebase divider is calcul ated using the following formula: eediv = int [ reference frequency (hz) 35 10 ?6 + 0.5 ] this value is written to the eeprom tim ebase divider r egister (eedivh and eedivl) or programmed into the eeprom timebase divider non- volatile register prior to any eepr om program or eras e operations (see 5.5 eeprom configuration and 5.11.3.1 eeprom timebase divider non-volatile register ). 5.7 eeprom security options the eeprom has a special security option, enabled by programming the eeprtct bit to 0 in the eepro m non-volatile register (eenvr). once security is enabled, the following limitati ons apply to the eeprom: the 16-byte eepro m locations from $08f0 to $08ff are protected from erase and program operations. the block erase and bulk erase m odes are disabled. byte erase can be used for all eeprom lo cations except $08f0 to $08ff. the eenvr is protected from further erase or program operations. 5.8 eeprom block protection the 512 bytes of eeprom is divided into four 128-byte blocks. each of these blocks can be protected from er ase/program operati ons by setting the eebpx bit in the eenvr. table 5-1 shows the addr ess ranges for the blocks.
eeprom technical data mc68hc908ab32 ? rev. 1.1 74 eeprom freescale semiconductor these bits are effective after a rese t or a read to ee nvr register. the block protect configurat ion can be modified by erasing/programming the corresponding bits in the eenvr register and then reading the eenvr register. 5.9 eeprom programming and erasing the unprogrammed or erased state of an eeprom bi t is a logic 1. the factory default for the eeprom array is $ff for all bytes. the programming operation changes an eeprom bit from logic 1 to logic 0 (programming cannot change a bit from logic 0 to a logic 1). in a single programming operation, t he minimum eeprom programming size is zero bits; the maxi mum is eight bits (one byte). the erase operation changes an eeprom bit from logi c 0 to logic 1. in a single erase operation, the minimum eeprom erase size is one byte; the maximum is the entire eeprom array. for each eeprom byte , the write/erase endur ance is 10,000 cycles. one write/erase cycle is defined as: a maximum of eight programming operations on the same byte followed by an erase operation of the that byte . therefore, it is possible to progr am a byte, bit by bit to logic 0 before requiring an erase on that byte. note: although programming a bit (from 0 or 1) with a logic 1 does not change the state of that bit, it is still regarded as a programming operation. that is, if the same byte is programmed ei ght times (with any value), that byte must be erased before it can be successfully programmed again. table 5-1. eeprom array address blocks block number (eebpx) address range eebp0 $0800?$087f eebp1 $0880?$08ff eebp2 $0900?$097f eebp3 $0980?$09ff
eeprom mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor eeprom 75 5.9.1 eeprom programming the unprogrammed or erased state of an eeprom bit is a logic 1. programming changes the state to a l ogic 0. only eeprom bytes in the non-protected blocks and the eenvr register can be programmed. use the following pr ocedure to program a byte of eeprom: 1. clear eeras1 and eeras0, and set eelat in the eecr. (a) 2. write the desire d data to the des ired eeprom address. (b) 3. set the eepgm bit. (c) go to step 7 if auto is set. 4. wait for a time, t eepgm , to program the byte. 5. clear eepgm bit. 6. wait for a time, t eefpv , for the programming voltage to fall. go to step 8. 7. poll the eepgm bit un til it is cleared by the internal timer. (d) 8. clear eelat bit. (e) note: a. eeras1 and eeras0 mu st be cleared for programming. setting the eelat bit configures the address and data buses to latch data for programming the array. only data wi th a valid eeprom address will be latched. if eelat is set, other writes to the ee cr will be allowed after a valid eeprom write. b. if more than one valid eeprom writes occur, the last address and data will be latched, overriding t he previous addre ss and data. once written data to the desired addr ess, do not read eeprom locations other than the written location. (reading an eep rom location returns the latched data, and causes t he read address to be latched.) c. the eepgm bit cannot be set if the eelat bit is cleared or a non- valid eeprom address is latched. this is to ensure proper programming sequence. once eepgm is set, do not r ead any eeprom locations, otherwise the current program cyc le will be unsuccessful. when eepgm is set, th e on-board programmi ng sequence will be activated.
eeprom technical data mc68hc908ab32 ? rev. 1.1 76 eeprom freescale semiconductor d. the delay time for the eepgm bit to be cleare d in auto mode is less than t eepgm . however, on other mcus, this delay time may be different. for forward compatibility, softwa re should not make any dependency on this delay time. e. any attempt to clear both eepg m and eelat bits with a single instruction will only cl ear eepgm. this is to al low time for removal of high voltage from the eeprom array. 5.9.2 eeprom erasing the programmed state of an eeprom bi t is logic 0. erasing changes the state to a logic 1. only eeprom bytes in the non-protected blocks and eenvr register can be erased. use the following proced ure to erase a byte, block, or the entire eeprom: 1. configure eeras1 and e eras0 for byte, block, or bulk erase; set eelat in eecr. (a) 2. byte erase: write any dat a to the desired address. (b) block erase: write any data to an address within the desired block. (b) bulk erase: write any data to an address within the array. (b) 3. set the eepgm bit. (c) go to step 7 if auto is set. 4. wait for a time: t ebyte for byte erase; t eblock for block erase; t ebulk for bulk erase. 5. clear eepgm bit. 6. wait for a time, t eefpv , for the erasing voltage to fall. go to step 8. 7. poll the eepgm bit un til it is cleared by the internal timer. (d) 8. clear eelat bits. (e)
eeprom mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor eeprom 77 note: a. setting the eelat bit configures t he address and data buses to latch data for erasing the array. only valid eeprom addresses will be latched. if eelat is set, other writes to the ee cr will be allowed after a valid eeprom write. b. if more than one valid eeprom writes occur, the last address and data will be latched, overriding t he previous addre ss and data. once written data to the desired addr ess, do not read eeprom locations other than the written location. (reading an eep rom location returns the latched data, and causes t he read address to be latched.) eenvr is not affected by block or bulk erase. c. the eepgm bit cannot be set if the eelat bit is cleared or a non- valid eeprom address is latched. this is to ensure proper programming sequence. once eepgm is set, do not r ead any eeprom locations, otherwise the current erase cycle will be unsuccessful. when eepgm is set, the erase mode cannot be changed, and the on-board erasing sequence w ill be activated. d. the delay time for the eepgm bit to be cleared in auto mode is less than t ebyte / t eblock / t ebulk . however, on other mcus, this delay time may be different. for forward compat ibility, software should not make any dependency on this delay time. e. any attempt to clear both eepg m and eelat bits with a single instruction will only cl ear eepgm. this is to al low time for removal of high voltage from the eeprom array. 5.10 low power modes the wait and stop inst ructions can put th e mcu in low power consumption standby modes. 5.10.1 wait mode the wait instruction does not affect the eeprom. it is possible to start the program or erase sequence on the eeprom and put th e mcu in wait mode.
eeprom technical data mc68hc908ab32 ? rev. 1.1 78 eeprom freescale semiconductor 5.10.2 stop mode the stop instruction r educes the eepr om power consumption to a minimum. the stop instruction should not be executed while the programming and erasing s equence is in progress. if stop mode is entered while eelat and eepgm is set, the programming sequence will be sto pped and the programming voltage to the eeprom array re moved. the programming sequence will be restarted after leaving stop mode; access to the eeprom is only possible after the programming sequence has completed. if stop mode is entered while eel at and eepgm is cleared, the programming sequence will be terminated abruptly. in either case, the data integrit y of the eeprom is not guaranteed. 5.11 eeprom registers four i/o registers and three non-vola tile registers control program, erase, and options of the eeprom array. 5.11.1 eeprom control register this read/write register controls programming/er asing of the eeprom array. eedum ? dummy bit this read/write bit has no function. address: $fe1d bit 7654321bit 0 read: eedum 0 eeoff eeras1 eeras0 eelat auto eepgm write: reset:00000000 figure 5-2. eeprom c ontrol register (eecr)
eeprom mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor eeprom 79 eeoff ? eeprom power-off this read/write bit disables th e eeprom module for lower power consumption. any attempts to a ccess the array will give unpredictable results. reset clears this bit. 1 = disable eeprom array 0 = enable eeprom array eeras[1:0] ? erase/progr am mode select bits these read/write bits set the eras e modes. reset clears these bits. eelat ? eeprom latch control this read/write bit latches the address and data buses for programming the eeprom array. eelat c an not be cleared if eepgm is still set. reset clears this bit. 1 = buses configured for eeprom program or erase operation 0 = buses configured for normal operation auto ? automatic terminat ion of program/erase cycle when auto is set, eepgm is cl eared automatically after the program/erase cycle is termi nated by the internal timer. (see note d for 5.9.1 eeprom programming and 5.9.2 eeprom erasing .) 0 = automatic clear of eepgm is disabled 1 = automatic clear of eepgm is enabled table 5-2. eeprom pr ogram/erase mode select eebpx eeras1 eeras0 mode 0 0 0 byte program 0 0 1 byte erase 0 1 0 block erase 0 1 1 bulk erase 1 x x no erase/program x = don?t care
eeprom technical data mc68hc908ab32 ? rev. 1.1 80 eeprom freescale semiconductor eepgm ? eeprom progr am/erase enable this read/write bi t enables the internal charge pump and applies the programming/erasing voltage to t he eeprom array if the eelat bit is set and a write to a valid eepro m location has occurred. reset clears the eepgm bit. 1 = eeprom programming/erasing power switched on 0 = eeprom programming/eras ing power switched off note: writing 0s to both the eelat and eepgm bits with a single instruction will only clear eepgm. thi s is to allow time for the removal of high voltage. 5.11.2 eeprom array configuration register the eeprom array configur ation register config ures eeprom security and eeprom block protection. this read-only register is loaded with the cont ents of the eeprom non- volatile register (e envr) after a reset. con[3:1] ? unused eeprtct ? eeprom protection bit the eeprtct bit is used to enable the securi ty feature in the eeprom (see 5.7 eeprom security options ). 1 = eeprom security disabled 0 = eeprom security enabled address: $fe1f bit 7654321bit 0 read: con3 con2 con1 eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: contents of eenvr ($fe1c) figure 5-3. eeprom array conf iguration register (eeacr)
eeprom mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor eeprom 81 eebp[3:0] ? eeprom block protection bits these bits prevent blocks of eepr om array from being programmed or erased. 1 = eeprom array block is protected 0 = eeprom array block is unprotected 5.11.2.1 eeprom non-volatile register the contents of this register is loaded into the eeprom array configuration register (eeacr) after a reset. this register is eras ed and programmed in the same way as an eeprom byte. note: the eenvr is factory programmed with $10. 5.11.3 eeprom timebase divider register the 16-bit eeprom timebas e divider register c onsists of two 8-bit registers: eedivh and eediv l. the 11-bit value in this register is used to configure the timebase divi der circuit to obtain the 35 s timebase for eeprom control. block number (eebpx) address range eebp0 $0800?$087f eebp1 $0880?$08ff eebp2 $0900?$097f eebp3 $0980?$09ff address: $fe1c bit 7654321bit 0 read: con3 con2 con1 eeprtct eebp3 eebp2 eebp1 eebp0 write: reset: unaffected by reset; $ff when blank; factory programmed $10 note: non-volatile eeprom r egister; write by programming. figure 5-4. eeprom non-vo latile register (eenvr)
eeprom technical data mc68hc908ab32 ? rev. 1.1 82 eeprom freescale semiconductor these two read/write registers are re spectively loaded with the contents of the eeprom timebase divider non-volatile registers (eedivhnvr and eedivlnvr) after a reset. eedivsecd ? eepro m divider security disable this bit enables/disables the security feature of the eediv registers. when eediv security feature is enab led, the state of the registers eedivh and eedivl are locked (inclu ding this eedivs ecd bit). the eedivhnvr and eedivlnvr non-volatile memo ry registers are also protected from be ing erased/programmed. 1 = eediv security feature disabled 0 = eediv security feature enabled eediv[10:0] ? eeprom timebase prescaler these prescaler bits store the val ue of eediv which is used as the divisor to derive a timebase of 35 s from the selected reference clock source (cgmxclk or bus clock, see 6.5 configuratio n register 2 ) for the eeprom related internal timer and circuits. eediv[10:0] bits are readable at any time. they are writable when eelat=0 and eedivsecd=1. address: $fe1a bit 7654321bit 0 read: eedivsecd rrrreediv10eediv9eediv8 write: reset: contents of eedivhnvr ($fe10) figure 5-5. eeprom divi der register high (eedivh) address: $fe1b bit 7654321bit 0 read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: contents of eedivlnvr ($fe11) figure 5-6. eeprom divide r register low (eedivl)
eeprom mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor eeprom 83 the eediv value is calculated by the following formula: eediv = int [ reference frequency (hz) 35 10 ?6 + 0.5 ] where the result inside the bra cket is rounded down to the nearest integer value. for example, if the reference frequency is 4.9152mhz, the eediv value is 172. note: programming/erasing the eeprom with an impro per eediv value may result in data lost and reduce endurance of the eeprom device. 5.11.3.1 eeprom timebase divider non-volatile register the 16-bit eeprom timebase divider non-volatile re gister consists of two 8-bit registers: eedivhnvr and eedivln vr. the contents of these two registers are respectively loaded into the eeprom timebase divider registers, eedivh and eedivl , after a reset. these two registers are erased and programmed in the same way as an eeprom byte. address: $fe10 bit 7654321bit 0 read: eedivsecd rrrreediv10eediv9eediv8 write: reset: unaffected by reset; $ff when blank figure 5-7. eeprom divi der non-volatile regi ster high(eedivhnvr) address: $fe11 bit 7654321bit 0 read: eediv7 eediv6 eediv5 eediv4 eediv3 eediv2 eediv1 eediv0 write: reset: unaffected by reset; $ff when blank figure 5-8. eepro m divider non-volatile r egister low (eedivlnvr)
eeprom technical data mc68hc908ab32 ? rev. 1.1 84 eeprom freescale semiconductor these two registers are protected fr om erase and program operations if the eedivsecd is set to l ogic 1 in the eedivh (see 5.11.3 eeprom timebase divider register ), or programmed to a logic 1 in the eedivhnvr. note: once eedivsecd in t he eedivhnvr is program med to 0 and after a system reset, the eediv security feature is perma nently enabled because the eedivsecd bi t in the eedivh is always loaded with a 0 thereafter. once this security feature is ar med, erase and program operations are disabled for eedivhnvr and eedivlnvr. modifications to the eed ivh and eedivl register s are also disabled. therefore, care should be taken bef ore programming a value into the eedivhnvr.
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor configuration register (config) 85 technical data ? mc68hc908ab32 section 6. configuration register (config) 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 6.3 functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.4 configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.5 configuration register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.2 introduction this section describes the config uration registers, config1 and config2. the configuration register s enable or disable these options: low-voltage inhibi t (lvi) in stop mode lvi reset lvi module power stop mode recovery time (32 cgmxclk cycles or 4096 cgmxclk cycles) cop timeout period (2 18 ? 2 4 or 2 13 ? 2 4 cgmxclk cycles) stop instruction computer operating pr operly module (cop) eeprom reference clock source (cpu bus clock or cgmxclk)
configuration register (config) technical data mc68hc908ab32 ? rev. 1.1 86 configuration register (config) freescale semiconductor 6.3 functional description the configuration register s are used in the init ialization of various options. the configuratio n registers can be writt en once after each reset. all of the configur ation register bits are cleared during reset. since the various options affect the operation of the mcu, it is recommended that these registers be writ ten immediately after re set. the configuration registers are locate d at $001f and $003f. the conf iguration register may be read at anytime. 6.4 configuration register 1 lvistop ? lvi enable in stop mode bit when the lvipwrd bit is clear, se tting the lvistop bit enables the lvi to operate in stop mode. reset clears lvistop. (see section 21. low-voltage inhibit (lvi) .) 1 = lvi enabled during stop mode 0 = lvi disabled during stop mode lvirstd ? lvi reset disable bit lvirstd disables the reset signa l from the lvi module. (see section 21. low-vol tage inhibit (lvi) .) 1 = lvi module resets disabled 0 = lvi module resets enabled address: $001f bit 7654321bit 0 read: lvistop r lvirstd lvipwrd ssrec coprs stop copd write: reset:00000000 r=reserved figure 6-1. configurati on register 1 (config1)
configuration register (config) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor configuration register (config) 87 lvipwrd ? lvi power disable bit lvipwrd disables the lvi module. (see section 21. low-voltage inhibit (lvi) .) 1 = lvi module power disabled 0 = lvi module power enabled ssrec ? short stop recovery bit ssrec enables the cp u to exit stop mode with a delay of 32 cgmxclk cycles instead of a 4096 cgmxclk cycle delay. 1 = stop mode recovery after 32 cgmxclk cycles 0 = stop mode recovery after 4096 cgmxclk cycles note: if using an external crystal oscillator, do not set the ssrec bit. coprs ? cop rate select bit coprs selects the cop timeout pe riod. reset clears coprs. (see section 20. computer o perating properly (cop) .) 1 = cop timeout period is 2 18 ? 2 4 cgmxclk cycles 0 = cop timeout period is 2 13 ? 2 4 cgmxclk cycles stop ? stop instruction enable bit stop enables the stop instruction. 1 = stop inst ruction enabled 0 = stop instruction tr eated as illegal opcode copd ? cop disable bit copd disables the cop module. (see section 20. computer operating properly (cop) .) 1 = cop module disabled 0 = cop module enabled extra care should be ex ercised when using this emulation part for development of code to be run in rom ab, as or az parts that the options selected by setting the conf ig1 register match exactly the options selected on any ro m code request submitted. the enable/disable logic is not necessarily identical in all parts of the ab, as, and az famili es. if in doubt, check with your local field applications representative.
configuration register (config) technical data mc68hc908ab32 ? rev. 1.1 88 configuration register (config) freescale semiconductor 6.5 configuration register 2 eedivclk ? eeprom timebase divider clock select bit eedivclk selects the referenc e clock source for the eeprom timebase divider. (see section 5. eeprom .) 1 = cpu bus clock drives the eeprom ti mebase divider 0 = cgmxclk drives the eeprom timebase divider extra care should be ex ercised when using this emulation part for development of code to be run in rom ab, as or az parts that the options selected by setting the conf ig2 register match exactly the options selected on any ro m code request submitted. the enable/disable logic is not necessarily identical in all parts of the ab, as, and az famili es. if in doubt, check with your local field applications representative. address: $003f bit 7654321bit 0 read: r eedivclk rrrrrr write: reset: 0 r=reserved figure 6-2. configurati on register 2 (config2)
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 89 technical data ? mc68hc908ab32 section 7. central processor unit (cpu) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 7.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 7.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 7.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 7.7 cpu during break interrupt s . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 7.2 introduction the m68hc08 cpu (central proce ssor unit) is an enhanced and fully object-code-compatible vers ion of the m 68hc05 cpu. the cpu08 reference manual (freescale document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture.
central processor unit (cpu) technical data mc68hc908ab32 ? rev. 1.1 90 central processor unit (cpu ) freescale semiconductor 7.3 features object code fully upward-com patible with m68hc05 family 16-bit stack pointer with st ack manipulation instructions 16-bit index register with x-regi ster manipulation instructions 8-mhz cpu internal bus frequency 64k-byte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decim al (bcd) data handling modular architecture with exp andable internal bu s definition for extension of addressing range beyond 64k-bytes low-power stop and wait modes 7.4 cpu registers figure 7-1 shows the five cpu registers. cpu regist ers are not part of the memory map.
central processor unit (cpu) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 91 figure 7-1. cpu registers 7.4.1 accumulator the accumulator is a general-purpose 8- bit register. the cpu uses the accumulator to hold operands and th e results of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 bit 7654321bit 0 read: write: reset: unaffected by reset figure 7-2. accumulator (a)
central processor unit (cpu) technical data mc68hc908ab32 ? rev. 1.1 92 central processor unit (cpu ) freescale semiconductor 7.4.2 index register the 16-bit index register allows i ndexed addressing of a 64k-byte memory space. h is the upper byte of the index regi ster, and x is the lower byte. h:x is the conc atenated 16-bit index register. in the indexed addressi ng modes, the cpu uses the contents of the index register to determine the conditional addr ess of the operand. the index register can serve also as a temporary data storage location. 7.4.3 stack pointer the stack pointer is a 16-bi t register that contains the address of the next location on the stack. during a rese t, the stack pointer is preset to $00ff. the reset stack pointer (rsp ) instruction sets the least significant byte to $ff and does not af fect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bi t offset and 16-bit offs et addressing modes, the stack pointer can functi on as an index register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. bit 15 1413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 7-3. index register (h:x)
central processor unit (cpu) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 93 note: the location of the stack is arbitr ary and may be relocated anywhere in ram. moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, t he stack pointer must point only to ram locations. 7.4.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter autom atically increm ents to the next sequential memory location every time an instruct ion or operand is fetched. jump, branch, and interr upt operations l oad the program counter with an addr ess other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vect or address is the address of the first instruction to be executed after exiti ng the reset state. 7.4.5 condition code register the 8-bit condition code register cont ains the interrupt mask and five flags that indicate the re sults of the instruction just executed. bits 6 and bit 15 1413121110987654321 bit 0 read: write: reset:0000000011111111 figure 7-4. stack pointer (sp) bit 15 1413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 7-5. prog ram counter (pc)
central processor unit (cpu) technical data mc68hc908ab32 ? rev. 1.1 94 central processor unit (cpu ) freescale semiconductor 5 are set permanently to logic 1. the following paragraphs describe the functions of the cond ition code register. v ? overflow flag the cpu sets the overfl ow flag when a two's complement overflow occurs. the signed branch instructi ons bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry fl ag when a carry occurs between accumulator bits 3 and 4 during an add-without-car ry (add) or add- with-carry (adc) operat ion. the half-carry flag is required for binary- coded decimal (bcd) arithmetic oper ations. the daa instruction uses the states of the h and c flags to determine t he appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 7-6. condition code register (ccr)
central processor unit (cpu) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 95 i ? interrupt mask when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are ena bled when the interrupt mask is cleared. when a cpu in terrupt occurs, the interrupt mask is set automatically after t he cpu registers are sa ved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note: to maintain m6805 family compatibility, the upper byte of the index register (h) is not sta cked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is clear ed, the highest-priority interrupt request is serviced first. a return-from-interrupt (rti) instru ction pulls the cp u registers from the stack and restores the interr upt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmet ic operation, logic operation, or data manipul ation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulati on produces a result of $00. 1 = zero result 0 = non-zero result
central processor unit (cpu) technical data mc68hc908ab32 ? rev. 1.1 96 central processor unit (cpu ) freescale semiconductor c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 7.5 arithmetic/l ogic unit (alu) the alu performs the arit hmetic and logic operat ions defined by the instruction set. refer to the cpu08 reference manual (freescale document order number cpu08rm/ad) for a descripti on of the instructions and addressing modes and more detail about the architectu re of the cpu. 7.6 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 7.6.1 wait mode the wait instruction: clears the interrupt ma sk (i bit) in the condi tion code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock
central processor unit (cpu) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 97 7.6.2 stop mode the stop instruction: clears the interrupt ma sk (i bit) in the condi tion code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. afte r exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, t he cpu clock begins running after the oscillator stabilization delay. 7.7 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: loading the instruction regist er with the swi instruction loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of t he cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and retu rns the mcu to normal operation if the break interrupt has been deasserted. 7.8 instruction set summary 7.9 opcode map see table 7-2 .
central processor unit (cpu) technical data mc68hc908ab32 ? rev. 1.1 98 central processor unit (cpu ) freescale semiconductor table 7-1. instr uction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) ?? ? ??? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) ?? ? ??? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ? ?? ??? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ? ?? ??? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ? ? ? ? ? ? rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 c b0 b7 0 b0 b7 c
central processor unit (cpu) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 99 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v ) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ? ? ? ? ? ? rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ? ? ? ? ? ? rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 table 7-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) technical data mc68hc908ab32 ? rev. 1.1 100 central processor unit (cpu ) freescale semiconductor brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 table 7-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 101 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? ?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ? ?? ??? imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? ??? inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ? ?? ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? ?? inh 52 7 table 7-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) technical data mc68hc908ab32 ? rev. 1.1 102 central processor unit (cpu ) freescale semiconductor eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ? ?? ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? ?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ? ?? ??? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 table 7-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0
central processor unit (cpu) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 103 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ? ??0 ?? dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? ?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ? ?? ??? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ? ? ? ? ? ? inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ? ? ? ? ? ? inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp) ? 1 ??????inh 87 2 pshh push h onto stack push (h); sp (sp) ? 1 ??????inh 8b 2 pshx push x onto stack push (x); sp (sp) ? 1 ??????inh 89 2 pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ? ?? ??? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 table 7-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc b0 b7 c 0 c b0 b7
central processor unit (cpu) technical data mc68hc908ab32 ? rev. 1.1 104 central processor unit (cpu ) freescale semiconductor ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ? ?? ??? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) ?????? inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? ?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? ?? ? dir 35 dd 4 stop enable irq pin; stop oscillator i 0; stop oscillator ? ? 0 ? ? ? inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? ?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 table 7-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc b0 b7 c
central processor unit (cpu) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 105 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) ?????? inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ? ? ? ? ? ? inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? ?? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 table 7-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) technical data mc68hc908ab32 ? rev. 1.1 106 central processor unit (cpu ) freescale semiconductor a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with post increment addressi ng mode rr relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer, 8-bit offset addressing mode ext extended addressing mode sp2 stack point er 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct destination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increm ent to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, post increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location ? set or cleared n negative bit ? not affected table 7-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 107 central processor unit (cpu) table 7-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1234569e6789abcd9ede9eef 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4sp2 3 sub 2ix1 4 sub 3sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4sp2 3 cmp 2ix1 4 cmp 3sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4sp2 3 sbc 2ix1 4 sbc 3sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4sp2 3 cpx 2ix1 4 cpx 3sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4sp2 3 and 2ix1 4 and 3sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4sp2 3 bit 2ix1 4 bit 3sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4sp2 3 lda 2ix1 4 lda 3sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4sp2 3 sta 2ix1 4 sta 3sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4sp2 3 eor 2ix1 4 eor 3sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4sp2 3 adc 2ix1 4 adc 3sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4sp2 3 ora 2ix1 4 ora 3sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4sp2 3 add 2ix1 4 add 3sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4sp2 3 ldx 2ix1 4 ldx 3sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4sp2 3 stx 2ix1 4 stx 3sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb
central processor unit (cpu) technical data mc68hc908ab32 ? rev. 1.1 108 central processor unit (cpu ) freescale semiconductor
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 109 technical data ? mc68hc908ab32 section 8. system integration module (sim) 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . 112 8.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 8.3.2 clock start-up from por or lvi reset . . . . . . . . . . . . . . . 113 8.3.3 clocks in stop and wait modes . . . . . . . . . . . . . . . . . . . . . 113 8.4 reset and system initiali zation. . . . . . . . . . . . . . . . . . . . . . . . 113 8.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8.4.2 active resets from in ternal sources . . . . . . . . . . . . . . . . . 114 8.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 8.4.2.2 computer operati ng properly (cop) rese t. . . . . . . . . . 116 8.4.2.3 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.4.2.4 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . .117 8.4.2.5 low-voltage inhibit (lvi) reset . . . . . . . . . . . . . . . . . . . 117 8.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.5.1 sim counter during power-on rese t. . . . . . . . . . . . . . . . . 118 8.5.2 sim counter during stop mode re covery . . . . . . . . . . . . . 118 8.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . . 118 8.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 8.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 8.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 8.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 8.6.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.6.3 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 8.6.4 status flag protection in break mode . . . . . . . . . . . . . . . . 123 8.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 8.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 8.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
system integration module (sim) technical data mc68hc908ab32 ? rev. 1.1 110 system integration module (sim) freescale semiconductor 8.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.8.1 sim break status regi ster . . . . . . . . . . . . . . . . . . . . . . . . . 127 8.8.2 sim reset status regi ster . . . . . . . . . . . . . . . . . . . . . . . . . 128 8.8.3 sim break flag control register . . . . . . . . . . . . . . . . . . . . 129 8.2 introduction this section describes the system integration module (sim), which supports up to 24 external and/or inte rnal interrupts. together with the cpu, the sim controls all mcu activi ties. a block diagram of the sim is shown in figure 8-1 . figure 8-2 is a summary of the sim i/o registers. the sim is a system state controller t hat coordinates cpu and exception timing. the sim is responsible for: bus clock generation and cont rol for cpu and peripherals: ? stop/wait/reset/bre ak entry and recovery ? internal clock control master reset control, includi ng power-on reset (por) and cop timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing modular architecture exp andable to 128 interrupt sources table 8-1 shows the internal signal names used in this section.
system integration module (sim) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 111 figure 8-1. sim block diagram table 8-1. signal naming conventions signal name description cgmxclk buffered version of osc1 from clock generator module (cgm) cgmvclk pll output cgmout pll-based or osc1-based clock output from cgm module (bus clock = cgmout divided by two) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to cgm) cgmout (from cgm) internal clocks master reset control reset pin logic lvi (from lvi module) illegal opcode (from cpu) illegal address (from address map decoders) cop (from cop module) interrupt sources cpu interface reset control sim counter cop clock cgmxclk (from cgm) 2
system integration module (sim) technical data mc68hc908ab32 ? rev. 1.1 112 system integration module (sim) freescale semiconductor 8.3 sim bus clock control and generation the bus clock generator provides system clock signal s for the cpu and peripherals on the mcu. the syst em clocks are generated from an incoming clock, cg mout, as shown in figure 8-3 . this clock can come from either an exter nal oscillator or from the on-chip pll. see section 9. clock generator module (cgm) . figure 8-3. cgm clock signals addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset:00000000 note: writing a l ogic 0 clears sbsw. $fe01 sim reset status register (srsr) read: por pin cop ilop ilad 0 lvi 0 write: por:10000000 $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 = unimplemented r = reserved figure 8-2. sim i/o register summary pll osc1 cgmxclk 2 bus clock generators sim cgm sim counter monitor mode clock select circuit cgmvclk bcs 2 a b s * cgmout * when s = 1, cgmout = b user mode ptc3
system integration module (sim) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 113 8.3.1 bus timing in user mode , the internal bus fr equency is either t he crystal oscillator output (cgmxclk) divided by four or the pll output (cgmvclk) divided by four. see section 9. clock generator module (cgm) . 8.3.2 clock start-up from por or lvi reset when the power-on reset module or the low-voltage inhibit module generates a reset, the clocks to the cpu and peripheral s are inactive and held in an inactive phase unt il after the 4096 cgmxclk cycle por timeout has been comp leted. the rst pin is driven low by the sim during this entire period. the ibus cl ocks start upon completion of the timeout. 8.3.3 clocks in stop and wait modes upon exit from stop mode (by an interrupt, brea k, or reset), the sim allows cgmxclk to clock the si m counter. the c pu and peripheral clocks do not become active until after the stop del ay timeout. this timeout is selectable as 4096 or 32 cgmxclk cycles. (see 8.7.2 stop mode .) in wait mode, t he cpu clocks are inactive. th e sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to see if t he module is active or i nactive in wait mode. some modules can be programmed to be active in wait mode. 8.4 reset and system initialization the mcu has the following reset sources: power-on reset module (por) external reset pin (rst ) computer operating pr operly module (cop) low-voltage inhi bit module (lvi) illegal opcode illegal address
system integration module (sim) technical data mc68hc908ab32 ? rev. 1.1 114 system integration module (sim) freescale semiconductor all of these resets produce the vector $fffe?ffff ($fefe?feff in monitor mode) and assert the internal reset signal (irst). irst causes all registers to be returned to thei r default values and all modules to be returned to thei r reset states. an internal reset clear s the sim counter (see 8.5 sim counter ), but an external reset does not. each of th e resets sets a co rresponding bit in the sim reset status register ( srsr). (see 8.8 sim registers .) 8.4.1 external pin reset pulling the asynchronous rst pin low halts all pr ocessing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for a minimum of 67 cg mxclk cycles, assuming t hat neither the por nor the lvi was the sour ce of the reset. see table 8-2 for details. figure 8-4 shows the relative timing. figure 8-4. extern al reset timing 8.4.2 active resets from internal sources all internal reset sources actively pull the rst pin low for 32 cgmxclk cycles to allow for resett ing of external periphe rals. the internal reset signal irst continues to be asse rted for an additional 32 cycles. see figure 8-5 . an internal reset can be caus ed by an illegal address, illegal opcode, cop timeout, lv i, or por. see figure 8-6 . note that for lvi or por resets, the sim cycles through 4096 cgmxclk cycles, during which the sim forces the rst pin low. the inter nal reset signal then follows the sequence from the falling edge of rst as shown in figure 8-5 . table 8-2. pin bit set timing reset type number of cycles required to set pin por/lvi 4163 (4096 + 64 + 3) all others 67 (64 + 3) rst iab pc vect h vect l cgmout
system integration module (sim) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 115 figure 8-5. internal reset timing the cop reset is asynchro nous to the bus clock. figure 8-6. sources of internal reset the active reset feature allows the par t to issue a reset to peripherals and other chips within a system built around the mcu. 8.4.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pul se to indicate that pow er-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 cgmxclk cycles. 64 cgmxclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, the foll owing events occur: a por pulse is generated the internal reset signal is asserted the sim enables cgmout internal clocks to the cpu and m odules are held i nactive for 4096 cgmxclk cycles to allow the oscillator to stabilize irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high cgmxclk illegal address rst illegal opcode rst coprst lvi por internal reset
system integration module (sim) technical data mc68hc908ab32 ? rev. 1.1 116 system integration module (sim) freescale semiconductor the rst pin is driven low during th e oscillator stabilization time the por bit of the sim reset status register (srsr) is set and all other bits in the register are cleared figure 8-7. por recovery 8.4.2.2 computer operat ing properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of the cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr). the sim actively pulls down the rst pin for all intern al reset sources. to prevent a cop module timeout, a va lue (any value) should be written to location $ffff. writing to loca tion $ffff clears t he cop counter and bits 12 through 4 of the sim coun ter. the sim counter output, which occurs at least every 2 13 ? 2 4 cgmxclk cycles, drives the cop counter. the cop should be serviced as soon as possible out of reset to guarantee the maximu m amount of time befor e the first timeout. the cop module is disabled if the rst pin or the irq pin is held at v tst while the mcu is in monitor m ode. the cop modul e can be disabled only through combinational logic conditioned with the high voltage signal on the rst or the irq pin. this prevents t he cop from becoming disabled as a result of external noise. during a break state, v tst on the rst pin disables the cop module. porrst osc1 cgmxclk cgmout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff
system integration module (sim) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 117 8.4.2.3 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bi t in the sim reset status register (srsr) and causes a reset. if the stop enable bit, stop, in t he configuration regi ster 1 (config1) is logic 0, the sim treats the stop instruction as an illegal opcode and causes an illegal opcode reset. the sim actively pulls down the rst pin for all internal reset sources. 8.4.2.4 illegal address reset an opcode fetch from an unm apped address genera tes an illegal address reset. the sim ve rifies that t he cpu is fetching an opcode prior to asserting the ilad bit in the si m reset status register (srsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. the sim acti vely pulls down the rst pin for all internal reset sources. 8.4.2.5 low-voltage inhibit (lvi) reset the low-voltage inhibit m odule (lvi) asserts its output to the sim when the v dd voltage falls to the trip voltage, v lvii . the lvi bit in the sim reset status register (srsr) is set, and the external reset pin (rst ) is held low while the sim counter counts out 4096 cgmxclk cycles . 64 cgmxclk cycles later, the cpu is released from reset to allow the reset vector sequence to occur. the sim actively pulls down the rst pin for all internal reset sources. 8.5 sim counter the sim counter is used by the pow er-on reset module (por) and in stop mode recovery to allow the os cillator time to stabilize before enabling the internal bus (i bus) clocks. the sim c ounter also serves as a prescaler for the computer operati ng properly (cop) module. the sim counter overflow supplies the cl ock for the cop module. the sim counter is 13 bits long and is clo cked by the falling edge of cgmxclk.
system integration module (sim) technical data mc68hc908ab32 ? rev. 1.1 118 system integration module (sim) freescale semiconductor 8.5.1 sim counter during power-on reset the power-on reset (por) module dete cts power appli ed to the mcu. at power-on, the por ci rcuit asserts the signal porrst. once the sim is initialized, it enabl es the clock generation m odule (cgm) to drive the bus clock state machine. 8.5.2 sim counter during stop mode recovery the sim counter is also used for stop mode recovery. the stop instruction clears the sim counter. af ter an interrupt, brea k, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the configuration register 1 (config1). if the ssrec bit is a logic 1, then the stop recovery is reduced from the normal delay of 4096 cgmxclk cycles down to 32 cgmxclk cycles. this is ideal for app lications using canned oscillators that do not require long st art-up times from stop mode. external crystal applications should use the full stop recovery time, that is, wi th ssrec cleared. 8.5.3 sim counter and reset states external reset has no effect on the sim counter. (see 8.7.2 stop mode for details.) the sim counter is free -running after all re set states. (see 8.4.2 active resets from internal sources for counter control and internal reset re covery sequences.) 8.6 exception control normal, sequential progra m execution can be chang ed in three different ways: interrupts ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) reset break interrupts
system integration module (sim) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 119 8.6.1 interrupts at the beginning of an interrupt, the cpu sa ves the cpu register contents onto the stack and sets the interrupt ma sk (i-bit) to prevent additional interrupts. at the end of an interrupt , the rti instruction recovers the cpu regist er contents from the stack so that normal processing can resume. figure 8-8 shows interrupt entry timing, and figure 8-9 shows interrupt recovery timing. figure 8-8. interrupt entry timing figure 8-9. interr upt recovery timing interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which ve ctor to fetch. once an interrupt is latched by the sim, no other interrup t may take precedence, regardless of priority, until the latched interrupt is serv iced (or the i-bit is cleared). (see figure 8-10 .) module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i-bit module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1[7:0] pc ? 1[15:8] opcode operand i-bit
system integration module (sim) technical data mc68hc908ab32 ? rev. 1.1 120 system integration module (sim) freescale semiconductor figure 8-10. in terrupt processing 8.6.1.1 hardware interrupts processing of a hardware interrupt begins after comp letion of the current instruction. when the inst ruction is complete, t he sim checks all pending hardware interrupts. if interrupts ar e not masked (i-bit clear in the condition code register), and if the corres ponding interrupt enable bit is set, the sim proceeds with interrup t processing; other wise, the next instruction is fetched and executed. no no no yes no no yes yes as many interrupts i bit set? from reset break i-bit set? irq interrupt? swi instruction? rti instruction? fetch next instruction unstack cpu registers stack cpu registers set i-bit load pc with interrupt vector execute instruction yes yes as exist on chip interrupt?
system integration module (sim) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 121 if more than one interrupt is pending at th e end of an instruction execution, the highest priority interrupt is serviced first. figure 8-11 demonstrates what hap pens when two interrupts are pending. if an interrupt is pending upon exit from the original inte rrupt service routine, the pending interrupt is serviced before the lda in struction is executed. figure 8-11. interrupt recognition example the lda opcode is pr efetched by both th e int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note: to maintain compatibility with the m6805 family, the h register is not pushed on the stack during in terrupt entry. if the in terrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prio r to exiting the routine. 8.6.1.2 swi instruction the swi instruction is a non-maskable instruct ion that causes an interrupt regardless of the state of the interrupt mask (i-bit) in the condition code register. note: a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine
system integration module (sim) technical data mc68hc908ab32 ? rev. 1.1 122 system integration module (sim) freescale semiconductor table 8-3. vector addresses vector priority address vector lowest $ffd0 adc conversion complete vector (high) $ffd1 adc conversion complete vector (low) $ffd2 keyboard vector (high) $ffd3 keyboard vector (low) $ffd4 sci transmit vector (high) $ffd5 sci transmit vector (low) $ffd6 sci receive vector (high) $ffd7 sci receive vector (low) $ffd8 sci error vector (high) $ffd9 sci error vector (low) $ffda reserved $ffdb reserved $ffdc reserved $ffdd reserved $ffde timer b channel 3 vector (high) $ffdf timer b channel 3 vector (low) $ffe0 timer b channel 2 vector (high) $ffe1 timer b channel 2 vector (low) $ffe2 spi transmit vector (high) $ffe3 spi transmit vector (low) $ffe4 spi receive vector (high) $ffe5 spi receive vector (low) $ffe6 timer b overflow vector (high) $ffe7 timer b overflow vector (low) $ffe8 timer b channel 1 vector (high) $ffe9 timer b channel 1 vector (low) $ffea timer b channel 0 vector (high) $ffeb timer b channel 0 vector (low) $ffec timer a overflow vector (high) $ffed timer a overflow vector (low) $ffee timer a channel 3 vector (high) $ffef timer a channel 3 vector (low) $fff0 timer a channel 2 vector (high) $fff1 timer a channel 2 vector (low) $fff2 timer a channel 1 vector (high) $fff3 timer a channel 1 vector (low) $fff4 timer a channel 0 vector (high) $fff5 timer a channel 0 vector (low) $fff6 programmable interrupt timer (high) $fff7 programmable interrupt timer (low) $fff8 pll vector (high) $fff9 pll vector (low) $fffa irq vector (high) $fffb irq vector (low) $fffc swi vector (high) $fffd swi vector (low) highest $fffe reset vector (high) $ffff reset vector (low)
system integration module (sim) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 123 8.6.2 reset all reset sources always have equal and highest pr iority and cannot be arbitrated. 8.6.3 break interrupts the break module can st op normal program flow at a software- programmable break point by asserti ng its break interrupt output. see section 22. break module (brk) . the sim puts the cpu into the break state by forcing it to the swi vector location. refer to the break interrupt subsection of each modul e to see how eac h module is affe cted by the break state. 8.6.4 status flag protection in break mode the sim controls whether status fl ags contained in ot her modules can be cleared during break m ode. the user can sele ct whether flags are protected from being clea red by properly initiali zing the break clear flag enable bit (bcfe) in t he sim break flag contro l register (sbfcr). protecting flags in break mode ensures that set flags will not be cleared while in break mode. this protection allows registers to be freely read and written during break mo de without losing stat us flag information. setting the bcfe bit e nables the clearing mechani sms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a two-step cleari ng mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal.
system integration module (sim) technical data mc68hc908ab32 ? rev. 1.1 124 system integration module (sim) freescale semiconductor 8.7 low-power modes executing the stop or wait instru ction puts the mcu in a low-power- consumption mode for st andby situations. the s im holds the cpu in a non-clocked state. the operation of eac h of these mode s is described below. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 8.7.1 wait mode in wait mode, t he cpu clocks are inactive while the peripheral clocks continue to run. figure 8-12 shows the timing fo r wait mode entry. a module that is active during wa it mode can wake up the cpu with an interrupt if the interrupt is enabled . stacking for the interrupt begins one cycle after the wait instruction duri ng which the interr upt occurred. in wait mode, the cpu clocks are i nactive. refer to the wait mode subsection of each module to see if th e module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode can also be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the sim break status register (sbsr). if the cop disable bit, copd, in the configuration register 1 (config1) is 0, then the computer operating properly (cop) module is enabled and remains active in wait mode. figure 8-12. wait mode entry timing figure 8-13 and figure 8-14 show the timing for wait recovery. wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or the wait opcode, depending on the last instruction.
system integration module (sim) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 125 figure 8-13. wait recovery from interrupt or break figure 8-14. wait recover y from internal reset 8.7.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for inte rrupts begins after the selected stop recovery time has elapsed. reset or break al so causes an exit from stop mode. the sim disables the clock gene rator module outputs (cgmout and cgmxclk) in stop mode, stopping the cpu and peri pherals. stop recovery time is selectable using the ssrec bit in the configuration register 1 (config1). if ssrec is set, stop recovery is reduced from the normal delay of 4096 cgmxclk cycles down to 32. this is ideal for applications using canned oscillators that do not require long start-up times from stop mode. note: external crystal applicati ons should use the full stop recovery time by clearing the ssrec bit. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 cgmxclk 32 cycles 32 cycles
system integration module (sim) technical data mc68hc908ab32 ? rev. 1.1 126 system integration module (sim) freescale semiconductor a break interrupt during stop mode sets the si m break stop/wait bit (sbsw) in the sim break st atus register (sbsr). the sim counter is held in reset from the execution of the stop instruction until th e beginning of stop recovery. it is then used to time the recovery period. figure 8-15 shows stop mode entry timing. figure 8-15. stop mode entry timing figure 8-16. stop mode recovery from interrupt or break stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or the stop opcode, depending on the last instruction. cgmxclk int/break iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period
system integration module (sim) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 127 8.8 sim registers the sim has three memo ry mapped registers. table 8-4 shows the mapping of thes e registers. 8.8.1 sim break status register the sim break status register (sbsr) contains a flag to indicate that a break caused an exit fr om stop or wait mode. sbsw ? sim br eak stop/wait this status bit is useful in applications requiring a return to stop or wait mode after exiting from a break interrupt. sbsw can be cleared by writing a logic 0 to it . reset clears sbsw. 1 = stop or wait mode was exited by break interrupt 0 = stop or wait mode was no t exited by break interrupt sbsw can be read within the break state swi r outine. the user can modify the return address on the st ack by subtractin g one from it. the following code is an example of this. table 8-4. sim registers address register access mode $fe00 sbsr user $fe01 srsr user $fe03 sbfcr user address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note (1) reset:00000000 r= reserved note: 1. writing a logic 0 clears sbsw. figure 8-17. sim break st atus register (sbsr)
system integration module (sim) technical data mc68hc908ab32 ? rev. 1.1 128 system integration module (sim) freescale semiconductor 8.8.2 sim reset status register this register contains six flags that show the source of the last reset. the sim reset status r egister can be clea red by reading it. a power-on reset sets the por bit and clears all other bits in the register. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if stop or wait mode was exited by break. tst lobyte,sp ; if returnlo is not 0, bne dolo ; then just decrement low byte. dec hibyte,sp ; else deal with high byte, too. dolo dec lobyte,sp ; point to stop/wait opcode. return pulh rti ; restore h register. address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad 0 lvi 0 write: reset:10000000 = unimplemented figure 8-18. sim reset status register (srsr)
system integration module (sim) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 129 pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr cop ? computer operati ng properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address rese t bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr lvi ? low-voltage i nhibit reset bit 1 = last reset was caused by the lvi circuit 0 = por or read of srsr 8.8.3 sim break flag control register the sim break control regist er contains a bit that enables software to clear status bits while t he mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear st atus bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, t he bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 8-19. sim break flag c ontrol register (sbfcr)
system integration module (sim) technical data mc68hc908ab32 ? rev. 1.1 130 system integration module (sim) freescale semiconductor
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor clock generator module (cgm) 131 technical data ? mc68hc908ab32 section 9. clock generator module (cgm) 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 9.4.1 crystal oscillator circ uit . . . . . . . . . . . . . . . . . . . . . . . . . . .134 9.4.2 phase-locked loop (pll ) circuit . . . . . . . . . . . . . . . . . . . 135 9.4.2.1 pll circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 9.4.2.2 acquisition and tracking modes . . . . . . . . . . . . . . . . . . 136 9.4.2.3 manual and automatic pll b andwidth modes . . . . . . . 136 9.4.2.4 programming the pll . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.4.2.5 special programming exceptions . . . . . . . . . . . . . . . . . 139 9.4.3 base clock selector ci rcuit . . . . . . . . . . . . . . . . . . . . . . . . 140 9.4.4 cgm external connectio ns . . . . . . . . . . . . . . . . . . . . . . . . 140 9.5 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 9.5.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . 142 9.5.2 crystal amplifier ou tput pin (osc2) . . . . . . . . . . . . . . . . . 142 9.5.3 external filter capacitor pin (c gmxfc) . . . . . . . . . . . . . . 142 9.5.4 pll analog power pin (v dda ) . . . . . . . . . . . . . . . . . . . . . . 142 9.5.5 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . 142 9.5.6 crystal output frequency signal (cgmxclk) . . . . . . . . . 143 9.5.7 cgm base clock output (cgmout) . . . . . . . . . . . . . . . . . 143 9.5.8 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . . 143 9.6 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 9.6.1 pll control register (pctl) . . . . . . . . . . . . . . . . . . . . . . . 144 9.6.2 pll bandwidth control register (pbwc) . . . . . . . . . . . . . 146 9.6.3 pll programming regi ster (ppg) . . . . . . . . . . . . . . . . . . . 148 9.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 9.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
clock generator module (cgm) technical data mc68hc908ab32 ? rev. 1.1 132 clock generator module (cgm) freescale semiconductor 9.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 9.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 9.9 cgm during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.10 acquisition/lock time spec ifications . . . . . . . . . . . . . . . . . . . 151 9.10.1 acquisition/lock time definitions. . . . . . . . . . . . . . . . . . . .152 9.10.2 parametric influences on reacti on time. . . . . . . . . . . . . . 153 9.10.3 choosing a filter capac itor . . . . . . . . . . . . . . . . . . . . . . . . 154 9.10.4 reaction time calculat ion . . . . . . . . . . . . . . . . . . . . . . . . . 155 9.2 introduction this section describes the clock generator module (cgm). the cgm generates the crystal clo ck signal, cgmxclk, wh ich operates at the frequency of the crystal. the cgm also generates the base clock signal, cgmout, from which the system int egration module (sim) derives the system clocks. cgmout is based on ei ther the crystal clock divided by two or the phase-locked loop (pll) clock, cgmvcl k, divided by two. the pll is a frequency gener ator designed for use with 1mhz to 8mhz crystals or ceramic resonators. the pll can generate an 8mhz bus frequency without using a higher frequency crystal. 9.3 features features of the cgm include the following: phase-locked loop with output freque ncy in integer multiples of the crystal reference programmable hardware voltage-c ontrolled oscillator (vco) for low-jitter operation automatic bandwidth control mode for low-jitt er operation automatic frequency lock detector cpu interrupt on entry or exit from locked condition
clock generator module (cgm) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor clock generator module (cgm) 133 9.4 functional description the cgm consists of th ree major sub-modules: crystal oscillator circuit which generates the constant crystal frequency clock, cgmxclk. phase-locked loop (p ll) which generates the programmable vco frequency clock cgmvclk. base clock selector ci rcuit; this software-controlled circuit selects either cgmxclk divided by tw o or the vco clock cgmvclk divided by two, as the base cloc k cgmout. the sim derives the system clocks from cgmout. figure 9-1 shows the struct ure of the cgm. figure 9-1. cgm block diagram bcs phase detector loop filter frequency divider voltage controlled oscillator bandwidth control lock detector clock cgmxclk cgmout cgmvdv cgmvclk simoscen crystal oscillator interrupt control cgmint cgmrdv pll analog 2 cgmrclk select circuit lock auto acq vrs[7:4] pllie pllf mul[7:4] to sim, sci to sim monitor mode a b s* user mode *when s = 1, cgmout = b osc1 osc2 v dda cgmxfc v ss ptc3
clock generator module (cgm) technical data mc68hc908ab32 ? rev. 1.1 134 clock generator module (cgm) freescale semiconductor 9.4.1 crystal oscillator circuit the crystal oscillator circuit consis ts of an inverting amplifier and an external crystal. the osc1 pin is t he input to the amp lifier and the osc2 pin is the output. the simoscen si gnal from the sys tem integration module (sim) enables the cr ystal oscillator circuit. the cgmxclk signal is t he output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. cg mxclk is then buffered to produce cgmrclk, t he pll reference clock. cgmxclk can be used by other modul es which require precise timing for operation. the duty cycl e of cgmxclk is not guaranteed to be 50% and depends on external factors, including t he crystal and related external components. an externally generated cl ock can also feed the os c1 pin of the crystal oscillator circuit. for th is configuration, the external clock should be connected to the osc1 pin and t he osc2 pin allowed to float. addr.register name bit 7654321bit 0 $001c pll control register (pctl) read: pllie pllf pllon bcs 1111 write: reset:00101111 $001d pll bandwidth control register (pbwc) read: auto lock acq xld 0000 write: reset:00000000 $001e pll programming register (ppg) read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset:01100110 = unimplemented figure 9-2. cgm i/ o register summary
clock generator module (cgm) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor clock generator module (cgm) 135 9.4.2 phase-locked loop (pll) circuit the pll is a frequency gene rator that can operate in either acquisition mode or tracking mode, depending on the a ccuracy of the output frequency. the pll can change betw een acquisition and tracking modes either automat ically or manually. 9.4.2.1 pll circuits the pll consists of the following circuits: voltage-controlled oscillator (vco) modulo vco fr equency divider phase detector loop filter lock detector the operating range of the vco is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and cgmxfc noise. the vco frequency is bound to a range from roughly one-half to twice the center-of-range frequency, f vrs . modulating the voltage on the cg mxfc pin changes the frequency within this range. by design, f vrs is equal to the nom inal center-of-range frequency, f nom , (4.9152mhz) times a li near factor l, or (l)f nom . cgmrclk is the pll reference clock, a buffered versio n of cgmxclk. cgmrclk runs at a frequency f rclk , and is fed to the pll through a buffer. the buffer output is the final reference cl ock, cgmrdv, running at a frequency f rdv =f rclk . the vco?s output clock, cgmvclk, running at a frequency f vclk , is fed back through a programmable modul o divider. the modulo divider reduces the vco clock by a factor n. the divider ?s output is the vco feedback clock, cgmvdv, running at a frequency f vdv =f vclk /n. (see 9.4.2.4 programming the pll for more information). the phase detector then compares th e vco feedback clock, cgmvdv, with the final reference clock, cgmrdv. a correction pulse is generated based on the phase di fference between the two si gnals. the loop filter
clock generator module (cgm) technical data mc68hc908ab32 ? rev. 1.1 136 clock generator module (cgm) freescale semiconductor then slightly alters t he dc voltage on the external capacitor connected to cgmxfc based on the wi dth and direction of th e correction pulse. the filter can make fa st or slow correcti ons depending on its mode, described in 9.4.2.2 acquisition and tracking modes . the value of the external capacitor and the refer ence frequency determines the speed of the corrections and the stability of the pll. the lock detector compares the freque ncies of the vco feedback clock, cgmvdv, and the final reference clock, cgmrdv. therefore, the speed of the lock detector is directly proportional to t he final reference frequency f rdv . the circuit determines the mode of the pll and the lock condition based on this comparison. 9.4.2.2 acquisition and tracking modes the pll filter is manually or automatically conf igurable into one of two operating modes: acquisition mode ? in acquisition mo de, the filter can make large frequency corrections to the vco. th is mode is used at pll start- up or when the pll has suffer ed a severe noise hit and the resulting vco frequency is much different fr om the desired frequency. when in acqui sition mode, the acq bit is clear in the pll bandwidth cont rol register. see 9.6.2 pll bandwidth control register (pbwc) . tracking mode ? in tracking mode, the filter make s only small corrections to the frequency of t he vco. pll jitter is much lower in tracking mode, but the response to noise is also slower. the pll enters tracking mode wh en the vco frequency is nearly correct, such as when the pll is selected as the base clock source. see 9.4.3 base clock se lector circuit . the pll is automatically in tracking mode wh en not in acqui sition mode or when the acq bit is set. 9.4.2.3 manual and au tomatic pll bandwidth modes the pll can change the bandwidth or oper ational mode of the loop filter manually or automatically.
clock generator module (cgm) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor clock generator module (cgm) 137 in automatic bandwidth control mode (auto = 1), the lock detector automatically switches between acquisition and tracking modes. automatic bandwidth c ontrol mode is used also to determi ne when the vco clock, cgmvclk, is safe to us e as the source for the base clock, cgmout. see 9.6.2 pll bandwidth c ontrol register (pbwc) . if pll interrupts are enabled, th e software can wait for a pll interrupt request and then check the lock bit. if interrup ts are disabled, software can poll the lock bit cont inuously (during pll start-up, usually) or at periodic intervals. in either case, when the lo ck bit is set, the vco clock is safe to use as the source for the base clock. see 9.4.3 base clock selector circuit . if the vco is select ed as the source for the base clock and the lock bit is clear, the pll has suffered a seve re noise hit and the software must take appropriate ac tion, depending on the application. (see 9.7 interrupts for information and precautions on using interrupts). the following conditions apply when t he pll is in automatic bandwidth control mode: the acq bit (see 9.6.2 pll bandwidth control register (pbwc) ) is a read-only indicator of the mode of th e filter. (see 9.4.2.2 acquisition and tracking modes ) the acq bit is set when the vco fr equency is within a certain tolerance ? trk and is cleared when the vc o frequency is out of a certain tolerance ? unt . (see 9.10 acquisition/lock time specifications ) the lock bit is a read-only indica tor of the locked state of the pll. the lock bit is set when the vco frequency is within a certain tolerance ? lock and is cleared when the vco frequency is out of a certain tolerance ? unl . (see 9.10 acquisition/lock time specifications ) cpu interrupts can occur if enabl ed (pllie = 1) when the pll?s lock condition changes, toggli ng the lock bit. (see 9.6.1 pll control register (pctl) ) the pll also may operate in ma nual mode (auto = 0). manual mode is used by systems that do not requi re an indicator of the lock condition for proper operation. such systems typicall y operate well below f busmax
clock generator module (cgm) technical data mc68hc908ab32 ? rev. 1.1 138 clock generator module (cgm) freescale semiconductor and require fast start- up. the following conditions apply when in manual mode: acq is a writable control bit that controls t he mode of the filter. before turning on the pll in manual mode, the acq bit must be clear. before entering tracking mode (acq = 1), software must wait a given time, t acq (see 9.10 acquisition/lock time specifications ), after turning on the pll by setting pllon in the pll control regi ster (pctl). software must wait a given time, t al , after entering tracking mode before selecting the pll as the clock source to cgmout (bcs = 1). the lock bit is disabled. cpu interrupts from the cgm are disabled. 9.4.2.4 programming the pll the following procedure shows how to program the pll. note: the round function in t he following equations m eans that the real number should be round ed to the nearest integer number. 1. choose the desired bus frequency, f busdes . 2. calculate the desired vco frequ ency (four times the desired bus frequency). 3. choose a practical pll reference frequency, f rclk . 4. select a vco frequency multiplier, n. f vclkdes 4f busdes = n round f vclkdes f rclk --------------------- - ?? ?? =
clock generator module (cgm) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor clock generator module (cgm) 139 5. calculate and verify the adequacy of the vco and bus frequencies f vclk and f bus . 6. select a vco linear range multiplier, l. where f nom = 4.9152mhz 7. calculate and verify the ade quacy of the vco programmed center-of-range frequency f vrs . f vrs = (l)f nom 8. verify the choice of n and l by comparing f vclk to f vrs and f vclkdes . for proper operation, f vclk must be within the application?s tolerance of f vclkdes , and f vrs must be as close as possible to f vclk . note: exceeding the recommended ma ximum bus frequency or vco frequency can cause th e mcu to ?crash?. 9. program the pll r egisters accordingly: a. in the upper 4 bits of the pll programmi ng register (ppg), program the binary equivalent of n. b. in the lower 4 bits of the pll programmi ng register (ppg), program the binary equivalent of l. 9.4.2.5 special pr ogramming exceptions the programming method described in 9.4.2.4 programming the pll does not account for two possible except ions ? a value of zero for n or l is meaningless when used in the eq uations given. to account for these exceptions: f vclk nf rclk = f bus f vclk () 4 ? = l round f vclk f nom ------------ - ?? ?? =
clock generator module (cgm) technical data mc68hc908ab32 ? rev. 1.1 140 clock generator module (cgm) freescale semiconductor a zero value for n is interprete d exactly the same as a value of one. a zero value for l di sables the pll and prev ents its selection as the source for the base clock. (see 9.4.3 base clock selector circuit ) 9.4.3 base clock selector circuit this circuit is used to select either the crystal clock, cgmxclk, or the vco clock, cgmvclk, as the source of the ba se clock, cgmout. the two input clocks go thro ugh a transition control ci rcuit that waits up to three cgmxclk cycles and three cg mvclk cycles to change from one clock source to the other. duri ng this time, cgmout is held in stasis. the output of the transition co ntrol circuit is then divided by two to correct the duty cycle. therefore, the bus clo ck frequency, which is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (cgmxclk or cgmvclk). the bcs bit in the pll cont rol register (pctl) sele cts which clock drives cgmout. the vco clock c annot be selected as t he base clock source if the pll is not turned on. the pll cannot be turned off if the vco clock is selected. the pll cannot be tur ned on or off simultaneously with the selection or deselection of the vco clock. the vco clock also cannot be selected as the base clock source if the factor l is programmed to a zero. this value would set up a conditi on inconsistent with the operation of the pll, so that the pll would be disabled and the crystal clock would be forced as the source of the base clock. 9.4.4 cgm external connections in its typical confi guration, the cgm requ ires seven external components. five of thes e are for the crystal o scillator and two are for the pll. the crystal oscillator is normally connected in a pierce oscillator configuration, as shown in figure 9-3 . this figure show s only the logical representation of the internal components and ma y not represent actual circuitry. the oscillator conf iguration uses five components:
clock generator module (cgm) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor clock generator module (cgm) 141 crystal, x 1 fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s (optional) the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be r equired for all rang es of operation, especially with high frequency cryst als. refer to the crystal manufacturer?s data for more information. figure 9-3 also shows the exter nal components for the pll: bypass capacitor, c byp filter capacitor, c f care should be taken with routing in or der to minimize signal cross talk and noise. (see 9.10 acquisition/lock time specifications for routing information and more info rmation on the filter capacitor?s value and its effects on pll performance). figure 9-3. cgm external connections c 1 c 2 c f simoscen cgmxclk r b x 1 r s * c byp *r s can be zero (shorted) when used with higher-fre quency crystals. refer to manufacturer?s data. osc1 osc2 v ssa cgmxfc v dda v dd
clock generator module (cgm) technical data mc68hc908ab32 ? rev. 1.1 142 clock generator module (cgm) freescale semiconductor 9.5 i/o signals the following paragraphs descr ibe the cgm i/o signals. 9.5.1 crystal amplifier input pin (osc1) the osc1 pin is an input to the crystal oscillator amplifier. 9.5.2 crystal amplifier output pin (osc2) the osc2 pin is the output of the crystal oscillator inverting amplifier. 9.5.3 external filter capacitor pin (cgmxfc) the cgmxfc pin is required by the loop filter to fi lter out phase corrections. a small external capac itor is connected to this pin. note: to prevent noise problems, c f should be placed as close to the cgmxfc pin as possible, with minimum routing distances and no routing of other si gnals across the c f connection. 9.5.4 pll analog power pin (v dda ) v dda is a power pin used by the analog portions of the pll. the pin should be connected to the sa me voltage potential as the v dd pin. note: route v dda carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 9.5.5 oscillator enable signal (simoscen) the simoscen signal come s from the system int egration module (sim) and enables the osci llator and pll.
clock generator module (cgm) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor clock generator module (cgm) 143 9.5.6 crystal output frequency signal (cgmxclk) cgmxclk is the crystal o scillator output signal. it runs at the full speed of the crystal (f xclk ) and is generated di rectly from the crystal oscillator circuit. figure 9-3 shows only the logical rela tion of cgmxclk to osc1 and osc2 and may not represent the ac tual circuitry. the duty cycle of cgmxclk is unknown and may depend on the crystal and other external factors. also, the frequen cy and amplitude of cgmxclk can be unstable at start-up. 9.5.7 cgm base clock output (cgmout) cgmout is the clock output of the cgm. this signal goes to the sim, which generates the mcu clocks. cgmout is a 50% duty cycle clock running at twice the bus frequency. cgmout is software programmable to be either the oscillat or output (cgmxclk) divi ded by two or the vco clock (cgmvclk) divided by two. 9.5.8 cgm cpu interrupt (cgmint) cgmint is the interrupt signal generated by the pll lock detector. 9.6 cgm registers the following registers control and monitor operation of the cgm: pll control regi ster (pctl). (see 9.6.1 pll control register (pctl) ) pll bandwidth control register (pbwc). (see 9.6.2 pll bandwidth control register (pbwc) ) pll programming r egister (ppg). (see 9.6.3 pll programming register (ppg) ) figure 9-4 is a summary of the cgm registers.
clock generator module (cgm) technical data mc68hc908ab32 ? rev. 1.1 144 clock generator module (cgm) freescale semiconductor 9.6.1 pll control register (pctl) the pll control register contains t he interrupt enable a nd flag bits, the on/off switch, and the ba se clock selector bit. addr.register name bit 7654321bit 0 $001c pll control register (pctl) read: pllie pllf pllon bcs 1111 write: reset:00101111 $001d pll bandwidth control register (pbwc) read: auto lock acq xld 0000 write: reset:00000000 $001e pll programming register (ppg) read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset:01100110 = unimplemented notes: 1. when auto = 0, pllie is forced to logic zero and is read-only. 2. when auto = 0, pllf and lock read as logic zero. 3. when auto = 1, acq is read-only. 4. when pllon = 0 or vrs[7:4] = $0, bcs is forced to logic zero and is read-only. 5. when pllon = 1, the pll programming register is read-only. 6. when bcs = 1, pllon is forced set and is read-only. figure 9-4. cgm i/ o register summary address: $001c bit 7654321bit 0 read: pllie pllf pllon bcs 1111 write: reset:00101111 = unimplemented figure 9-5. pll cont rol register (pctl)
clock generator module (cgm) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor clock generator module (cgm) 145 pllie ? pll interrupt enable bit this read/write bi t enables the pll to gener ate an interrupt request when the lock bit toggles, sett ing the pll flag, pllf. when the auto bit in the pll bandwidth c ontrol register (pbwc) is clear, pllie cannot be written and reads as 0. reset clears the pllie bit. 1 = pll interrupts enabled 0 = pll interrupts disabled pllf ? pll interrupt flag bit this read-only bit is set wheneve r the lock bit toggles. pllf generates an interrupt request if th e pllie bit is set also. pllf always reads as 0 when the auto bi t in the pll bandwidth control register (pbwc) is clear. the pllf bit should be cleared by reading the pll control register. reset clears the pllf bit. 1 = change in lock condition 0 = no change in lock condition note: the pllf bit shoul d not be inadvertently cl eared. any read or read- modify-write operation on the pll cont rol register clear s the pllf bit. pllon ? pll on bit this read/write bit activates t he pll and enables the vco clock, cgmvclk. pllon cannot be cleared if the vco clock is driving the base clock, cgmout (bcs = 1). see 9.4.3 base clock selector circuit . reset sets this bit so that the loop can stabi lize as the mcu is powering up. 1 = pll on 0 = pll off bcs ? base clock select bit this read/write bit sele cts either the crystal oscillator output, cgmxclk, or the vco clock, cgm vclk, as the sour ce of the cgm output, cgmout. cgmout frequency is one-ha lf the frequency of the selected clock. bcs cannot be set while t he pllon bit is clear. after toggling b cs, it may take up to three cgmxclk and three cgmvclk cycles to complete the tr ansition from one source clock to
clock generator module (cgm) technical data mc68hc908ab32 ? rev. 1.1 146 clock generator module (cgm) freescale semiconductor the other. during the transition, cgmout is held in stasis. see 9.4.3 base clock sel ector circuit . reset and the stop instruction clear the bcs bit. 1 = cgmout driven by cgmvclk/2 0 = cgmout driven by cgmxclk/2 note: pllon and bcs have built-in protec tion that prevents the base clock selector circuit from se lecting the vco clock as the source of the base clock if the pll is of f. therefore, pllon cannot be cleared when bcs is set, and bcs cannot be set when pllon is clear. if the pll is off (pllon = 0), selecting cgmvclk require s two writes to the pll control register. see 9.4.3 base clock se lector circuit . bits [3:0] ? unimplemented bits these bits provide no functi on and always read as 1. 9.6.2 pll bandwidth control register (pbwc) the pll bandwidth control regi ster does the following: selects automatic or manual (software-controlled) bandwidth control mode indicates when the pll is locked in automatic bandwidth control mode , indicates when the pll is in acquisition or tracking mode in manual operation, forces the pll into acquisition or tracking mode. address: $001d bit 7654321bit 0 read: auto lock acq xld 0000 write: reset:00000000 = unimplemented figure 9-7. pll bandwidth control register (pbwc)
clock generator module (cgm) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor clock generator module (cgm) 147 auto ? automatic bandwidth control bit this read/write bit sele cts automatic or manual bandwidth control. when initializing the p ll for manual operation (auto = 0), the acq bit should be cleared before turni ng the pll on. reset clears the auto bit. 1 = automatic bandwidth control 0 = manual bandwidth control lock ? lock indicator bit when the auto bit is set, lock is a read-only bit that becomes set when the vco clock cgmvclk, is locked (running at the programmed frequency). when the auto bit is clear, lock reads as 0 and has no meaning. re set clears the lock bit. 1 = vco frequency correct or locked 0 = vco frequency inco rrect or unlocked acq ? acquisition mode bit when the auto bit is set, acq is a read-only bit that indicates whether the pll is in acquisition mode or tr acking mode. when the auto bit is clear, acq is a read/write bit that controls whether the pll is in acquisiti on or tracking mode. in automatic bandwidth control mode (auto = 1), the last-written value from manual operati on is stored in a te mporary location and is recovered when manual oper ation resumes. rese t clears this bit, enabling acquisition mode. 1 = tracking mode 0 = acquisition mode xld ? crystal loss detect bit when the vco output, cgmvclk, is driving cgmout, this read/write bit indi cates whether the crystal reference frequency is active or not. to check the status of the crystal reference, the following procedure should be followed: 1. write a 1 to xld. 2. wait 4 n cycles. (n is the vc o frequency multiplier.) 3. read xld. 1 = crystal refere nce is not active 0 = crystal reference is active
clock generator module (cgm) technical data mc68hc908ab32 ? rev. 1.1 148 clock generator module (cgm) freescale semiconductor the crystal loss detect function wor ks only when the bcs bit is set, selecting cgmvclk to drive cg mout. when bcs is clear, xld always reads as 0. bits [3:0] ? reserved for test these bits enable test functions not available in user mode. to ensure software portability fr om development systems to user applications, software should write zeros to bits [3:0] whenever writing to pbwc. 9.6.3 pll programming register (ppg) the pll programming regist er contains the program ming information for the modulo feedback divider and the programming information for the hardware configurat ion of the vco. mul[7:4] ? multip lier select bits these read/write bits control the m odulo feedback divider that selects the vco frequency multiplier, n. (see 9.4.2.1 pll circuits and 9.4.2.4 programming the pll ). a value of $0 in th e multiplier select bits configures the m odulo feedback divider th e same as a value of $1. reset initializes these bits to $6 to give a defaul t multiply value of 6. address: $001e bit 7654321bit 0 read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset:01100110 figure 9-8. pll program ming register (ppg)
clock generator module (cgm) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor clock generator module (cgm) 149 note: the multiplier select bits have built-in protection that prevents them from being written when the p ll is on (pllon = 1). vrs[7:4] ? vco r ange select bits these read/write bits control the hardware center-of-range linear multiplier l, which controls the hardware cent er-of-range frequency f vrs . (see 9.4.2.1 pll circuits , 9.4.2.4 programming the pll , and 9.6.1 pll control register (pctl) ). vrs[7:4] cannot be written when the pllon bit in the pll control register (pctl) is set. (see 9.4.2.5 special pr ogramming exceptions ). a value of $0 in the vco range select bits di sables the pll and clear s the bcs bit in the pctl. (see 9.4.3 base clock se lector circuit and 9.4.2.5 special programming exceptions for more informatio n). reset initializes the bits to $6 to gi ve a default range mu ltiply value of 6. note: the vco range select bits have built-i n protection that prevents them from being written when the pll is on (p llon = 1) and prevents selection of the vco clo ck as the source of the base clock (bcs = 1) if the vco range select bits are all clear. the vco range select bits must be programmed correctly. incorrect programming may result in failur e of the pll to achieve lock. table 9-1. vco frequency mu ltiplier (n) selection mul7:mul6:mul5:mul4 vco frequency multiplier (n) 0000 1 0001 1 0010 2 0011 3 1101 13 1110 14 1111 15
clock generator module (cgm) technical data mc68hc908ab32 ? rev. 1.1 150 clock generator module (cgm) freescale semiconductor 9.7 interrupts when the auto bit is set in the pll bandwidth control register (pbwc), the pll can generate a cpu interrupt request ev ery time the lock bit changes state. the pllie bit in the pll control register (pctl) enables cpu interrupts from the pll. pllf, the interrupt flag in the pctl, becomes set whether interrupts ar e enabled or not. when the auto bit is clear, cpu interrupts from the pll are disabl ed and pllf reads as 0. software should read the lock bit after a pll interrupt request to see if the request was due to an entry into lock or an exit fr om lock. when the pll enters lock, the vco clock cg mvclk, divided by two can be selected as the cgmout source by setting bcs in the pctl. when the pll exits lock, the vco clock fr equency is corrupt, and appropriate precautions should be taken. if the application is not frequency- sensitive, interrupts s hould be disabled to prevent pll interrupt service routines from impedi ng software performance or from exceeding stack limitations. note: software can select cgmvclk/2 as the cgmout source even if the pll is not locked (lock = 0). therefor e, software should make sure the pll is locked before setting t he bcs bit. 9.8 low-power modes the wait and stop in structions put the mcu in low-power- consumption standby modes. 9.8.1 wait mode the wait instruction does not affect the cgm. before entering wait mode, software can disengage and turn off the pll by clearing the bcs and pllon bits in the pll control r egister (pctl). less power-sensitive applications can disengage the pll without turning it off. applications that require the pll to wake t he mcu from wait mode also can deselect the pll output wit hout turning off the pll.
clock generator module (cgm) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor clock generator module (cgm) 151 9.8.2 stop mode when the stop instruction execut es, the sim drives the simoscen signal low, disabling the cgm and holding low all cgm outputs (cgmxclk, cgmo ut, and cgmint). if the stop instruction is execut ed with the vco clock, cgmvclk, divided by two driving cg mout, the pll automatic ally clears the bcs bit in the pll control regi ster (pctl), thereby sele cting the crystal clock, cgmxclk, divided by two as the so urce of cgmout . when the mcu recovers from stop, th e crystal clock divided by two drives cgmout and bcs remains clear. 9.9 cgm during break interrupts the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the sim break flag contro l register (sbfcr) enabl es software to clear status bits during the break state. see section 8. system integration module (sim) . to allow software to clear status bits during a break interrupt, a 1 should be written to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the pllf bit durin g the break state, write a 0 to the bcfe bit. with bcfe at 0 (its def ault state), software can read and wr ite the pll control register during the break state without affecting t he pllf bit. 9.10 acquisition/lock time specifications the acquisition and lo ck times of the pll are, in many applications, the most critical pll desi gn parameters. proper desig n and use of the pll ensures the highest stability and lowest acquisi tion/lock times.
clock generator module (cgm) technical data mc68hc908ab32 ? rev. 1.1 152 clock generator module (cgm) freescale semiconductor 9.10.1 acquisition/lock time definitions typical control systems refer to the ac quisition time or lock time as the reaction time of t he system, within specified to lerances, to a step input. in a pll, the step input occurs when the pll is turned on or when it suffers a noise hit. the tolerance is usually specified as a percentage of the step input or when the output settles to t he desired value plus or minus a percentage of t he frequency change. ther efore, the reaction time is constant in this definition, regardless of the size of the step input. for example, consider a system with a 5% acquisition time tolerance. if a command instructs the system to change from 0hz to 1mhz, the acquisition time is the time tak en for the frequency to reach 1mhz 50khz. 50khz = 5% of the 1mhz step input. if the system is operating at 1mhz and suffers a ?100khz noise hit, the acquisi tion time is the time taken to return from 900khz to 1mhz 5khz. 5khz = 5% of the 100khz step input. other systems refer to ac quisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified toleranc es. therefore, the acquisition or lock time varies according to the original error in the output . minor errors may not even be registered. typical pll applications prefer to use this definition because the system requires the out put frequency to be within a certain tolerance of the desired fr equency regardless of the size of the initial error. the discrepancy in these definitions ma kes it difficult to specify an acquisition or lock time for a typical pll. therefor e, the definitions for acquisition and lock times for th is module are as follows: acquisition time, t acq , is the time the pll ta kes to reduce the error between the actual output fr equency and the desired output frequency to less than the tr acking mode entry tolerance ? trk . acquisition time is based on an initial frequency error, (f des ? f orig )/f des , of not more than 100%. in automatic bandwidth control mode (see 9.4.2.3 manual and automatic pll bandwidth modes ), acquisition time expires when the acq bit becomes set in the pll bandwid th control regi ster (pbwc).
clock generator module (cgm) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor clock generator module (cgm) 153 lock time, t lock , is the time the pll ta kes to reduce the error between the actual output fr equency and the desired output frequency to less than the lock mode entry tolerance ? lock . lock time is based on an init ial frequency error, (f des ? f orig )/f des , of not more than 100%. in automatic bandwidth control mode, lock time expires when the lock bit becomes se t in the pll bandwidth control regi ster (pbwc). see 9.4.2.3 manual and automatic pll bandwidth modes . obviously, the acquisition and lock ti mes can vary according to how large the frequency error is and may be shorter or longer in many cases. 9.10.2 parametric influences on reaction time acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. these reaction times are not constant, however. many factors di rectly and indirect ly affect the acquisition time. the most critical parameter which af fects the reaction times of the pll is the reference frequency, f rdv . this frequency is the input to the phase detector and controls how often the pll makes corr ections. for stability, the corrections must be small compared to t he desired frequency, so several corrections are requir ed to reduce the frequency error. therefore, the slower the reference the longer it takes to make these corrections. this parameter is also un der user control via the choice of crystal frequency f xclk . another critical parameter is the external filter capacitor. the pll modifies the voltage on the vco by adding or subtracting charge from this capacitor. therefore, the rate at which t he voltage changes for a given frequency error (thus change in charge) is propo rtional to the capacitor size. the si ze of the capa citor also is related to the stability of the pll. if the capacitor is too small, the pl l cannot make small enough adjustments to the volt age and the system cannot lo ck. if the capacitor is too large, the pl l may not be able to ad just the voltage in a reasonable time. see 9.10.3 choosing a filter capacitor .
clock generator module (cgm) technical data mc68hc908ab32 ? rev. 1.1 154 clock generator module (cgm) freescale semiconductor also important is th e operating voltage po tential applied to v dda . the power supply potential alters the charac teristics of the p ll. a fixed value is best. variable supplies, such as bat teries, are acceptable if they vary within a known range at very slow speeds. noise on the power supply is not acceptable, because it caus es small frequency errors which continually change the acquisi tion time of the pll. temperature and processing also can af fect acquisition time because the electrical characteristics of the pll change. the part operates as specified as long as these influences stay within the specified limits. external factors, however, can caus e drastic changes in the operation of the pll. these factors include noise injected into t he pll through the filter capacitor, filter capacitor leakage, stray impedanc es on the circuit board, and even hum idity or circuit board contamination. 9.10.3 choosing a filter capacitor as described in 9.10.2 parametric infl uences on reaction time , the external filter capacitor c f is critical to the stabili ty and reacti on time of the pll. the pll is also dependent on reference frequency and supply voltage. the value of t he capacitor must, ther efore, be chosen with supply potential and reference fre quency in mind. for proper operation, the external filter capac itor must be chosen a ccording to the following equation: for the value of v dda , the voltage potential at which the mcu is operating should be used. if the power supply is va riable, choose a value near the middle of the range of possible supply values. this equation does not always yield a commonl y available capacitor size, so round to t he nearest available size. if the value is between two different sizes, choose the higher va lue for better stability. choosing the lower size may seem attractive for acquisition time impr ovement, but the pll may become unstable. also, alwa ys choose a capacitor with a tight tolerance ( 20% or better) and low dissipation. c f c fact v dda f rdv ------------ - ?? ?? =
clock generator module (cgm) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor clock generator module (cgm) 155 9.10.4 reaction time calculation the actual acquisition and lock time s can be calculated using the equations below. these equations yield nominal values under the following conditions: correct selection of filter capacitor, c f , (see 9.10.3 choosing a filter capacitor ) room temperature operation negligible external leakage on cgmxfc negligible noise the k factor in the equatio ns is derived from in ternal pll parameters. k acq is the k factor when the pll is configured in acquisition mode, and k trk is the k factor when the pll is configured in tracking mode. see 9.4.2.2 acquisiti on and tracking modes . note the inverse proportionality bet ween the lock time and the reference frequency. in automatic bandwidth control mode the acquisi tion and lock times are quantized into units based on th e reference frequency. see 9.4.2.3 manual and automatic pll bandwidth modes . a certain number of clock cycles, n acq , is required to ascertain w hether the pll is within the tracking mode entry tolerance ? trk , before exiting acquisition mode. also, a certain number of clock cycles, n trk , is required to ascertain t acq v dda f rdv ------------ - ?? ?? 8 k acq ------------- ?? ?? = t al v dda f rdv ------------ - ?? ?? 4 k trk ------------ ?? ?? = t lock t acq t al + =
clock generator module (cgm) technical data mc68hc908ab32 ? rev. 1.1 156 clock generator module (cgm) freescale semiconductor whether the pll is within the lock mode entry tolerance ? lock . therefore, the acquisition time t acq , is an integer multiple of n acq /f rdv , and the acquisition to lock time t al , is an integer multiple of n trk /f rdv . also, since the average frequency over the enti re measurement period must be within the specif ied tolerance, the total time usually is longer than t lock as calculated above. in manual mode, it is us ually necessary to wait considerably longer than t lock before selecting t he pll clock (see 9.4.3 base clock selector circuit ), because the factors described in 9.10.2 parametric influences on reaction time may slow the lock time considerably.
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 157 technical data ? mc68hc908ab32 section 10. monitor rom (mon) 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 10.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 10.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 10.4.3 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 10.4.4 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 10.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 10.4.6 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 10.5 security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 10.6 extended security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 10.2 introduction this section describes the moni tor rom (mon). the monitor rom allows complete testing of the mcu through a single-wire interface with a host computer.
monitor rom (mon) technical data mc68hc908ab32 ? rev. 1.1 158 monitor rom (mon) freescale semiconductor 10.3 features features of the monitor rom include the following: normal user-mode pin functionality one pin dedicated to serial co mmunication between monitor rom and host computer standard mark/space non-return -to-zero (nrz) communication with host computer 4800 baud to 28.8 k-baud comm unication with host computer flash memory security feature 1 execution of code in ram or flash 10.4 functional description the monitor rom receives and exec utes commands from a host computer. figure 10-1 shows a example circui t used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. while simple monitor co mmands can access any memory address, the mcu has a flash security feature to prevent external viewing of the contents of fl ash. proper procedures must be followed to verify flash content. access to the fla sh is denied to unauthorized users of customer specified software. in monitor mode, the mcu can execute host-co mputer code in ram while all mcu pins except pta0 reta in normal operati ng mode functions. all communication between the host computer and t he mcu is through the pta0 pin. a level-shifting and multiplexing interface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and require s a pullup resistor. 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the flash difficult for unauthorized users.
monitor rom (mon) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 159 figure 10-1. moni tor mode circuit + + + + 10 m ? x1 v dd v tst mc145407 mc74hc125 rst irq osc1 osc2 v ss v dd pta0 v dd 10 k ? 0.1 f 10 ? 6 5 2 4 3 1 db-25 2 3 7 20 18 17 19 16 15 v dd v dd v dd 20 pf 20 pf 10 f 10 f 10 f 10 f 1 2 4 7 14 3 0.1 f 4.9152 mhz 10 k ? ptc3 v dd 10 k ? b a notes: position b ? bus clock = cgmxclk 2 (see notes) 5 6 ptc0 ptc1 v dd 10 k ? position a ? bus clock = cgmxclk 4 or cgmvclk 4 v cgmxfc 0.1 f v dd a v dd a mc68hc908ab32
monitor rom (mon) technical data mc68hc908ab32 ? rev. 1.1 160 monitor rom (mon) freescale semiconductor 10.4.1 entering monitor mode table 10-1 shows the pin conditions for entering monitor mode. enter monitor mode by either executing a software inte rrupt instruction (swi) or applying a logic 0 and t hen a logic 1 to the rst pin. the mcu sends a break si gnal (10 consecutive lo gic 0s) to the host computer, indicating that it is ready to receive a command. the break signal also provides a timing referenc e to allow the host to determine the necessary baud rate. monitor mode uses alternat e vectors for reset, sw i, and break interrupt. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. the cop module is disabled in monitor mode as long as v tst (see section 23. electri cal specifications ) is applied to either the irq pin or the rst pin. (see section 8. system in tegration module (sim) for more information on modes of operation.) note: holding the ptc3 pin low when ent ering monitor mode causes a bypass of a divide-by-two stage at the oscillator. the cgmout frequency is equal to the cgmxclk frequency, and the osc1 i nput directly generates internal bus clocks. in th is case, the osc1 signal must have a 50% duty cycle at maximum bus frequency. table 10-1. monitor mode entry conditions irq pin ptc0 pin ptc1 pin pta0 pin ptc3 pin cgmout bus frequency (cgmout 2) v tst (1) notes : 1. for v tst , see section 23. electri cal specifications . 1011 cgmxclk 2 or cgmvclk 2 cgmxclk 4 or cgmvclk 4 v tst 1010 cgmxclk cgmxclk 2
monitor rom (mon) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 161 table 10-2 is a summary of the differ ences between user mode and monitor mode. 10.4.2 data format communication with the monitor rom is in standard non-return-to-zero (nrz) mark/space data format. (see figure 10-2 and figure 10-3 .) the data transmit and receive rate can be anywhere fr om 4800 baud to 28.8 k-baud. transmit and receive baud rates must be identical. figure 10-2. moni tor data format figure 10-3. sample monitor waveforms table 10-2. mode differences modes functions cop reset vector high reset vector low break vector high break vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd $fffc $fffd monitor disabled (1) notes : 1. if the high voltage (v tst ) is removed from the irq pin while in monitor mode, the sim asserts its cop enable output. the cop can be enabled or disabled by the copd bit in the configuration register 1 (config1). (see 23.6 5.0-v dc electrical characteristics .) $fefe $feff $fefc $fefd $fefc $fefd bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 start bit bit 0 bit 1 stop bit bit 2 $a5 break bit 3 bit 4 bit 5 bit 6 bit 7
monitor rom (mon) technical data mc68hc908ab32 ? rev. 1.1 162 monitor rom (mon) freescale semiconductor 10.4.3 echoing as shown in figure 10-4 , the monitor rom immediately echoes each received byte back to the pt a0 pin for error checking. any result of a command appears after the ec ho of the last byte of the command. figure 10-4. read transaction 10.4.4 break signal a start bit followed by nine low bits is a break signal. (see figure 10-5 .) when the monitor receives a break sign al, it drives the pta0 pin high for the duration of tw o bits before echoi ng the break signal. figure 10-5. break transaction addr. high read read addr. high addr. low addr. low data echo sent to monitor result 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit two-stop-bit delay before zero echo
monitor rom (mon) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 163 10.4.5 commands the monitor rom uses these commands: read, read memory write, write memory iread, indexed read iwrite, indexed write readsp, read stack pointer run, run user program a sequence of iread or iwrite co mmands can access a block of memory sequentially over th e full 64k-byte memory map. table 10-3. read (r ead memory) command description read byte from memory operand specifies 2-byte address in high byte:low byte order data returned returns contents of specified address opcode $4a command sequence read read echo sent to monitor address high address high address low data return address low
monitor rom (mon) technical data mc68hc908ab32 ? rev. 1.1 164 monitor rom (mon) freescale semiconductor table 10-4. write (write memory) command description write byte to memory operand specifics 2-byte address in high byte:low byte order; low byte followed by data byte data returned none opcode $49 command sequence table 10-5. iread (i ndexed read) command description read next 2 bytes in memory from last address accessed operand specifies 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence write write echo sent to monitor address high address high address low address low data data iread iread echo sent to monitor data return data
monitor rom (mon) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 165 table 10-6. iwrite (i ndexed write) command description write to last address accessed + 1 operand specifies single data byte data returned none opcode $19 command sequence table 10-7. read sp (read stack pointer) command description reads stack pointer operand none data returned returns stack pointer in high byte:low byte order opcode $0c command sequence iwrite iwrite echo sent to monitor data data readsp readsp echo sent to monitor sp return sp high low
monitor rom (mon) technical data mc68hc908ab32 ? rev. 1.1 166 monitor rom (mon) freescale semiconductor 10.4.6 baud rate with a 4.9152-mhz crystal and the ptc3 pin at logic 1 during reset, data is transferred between t he monitor and host at 480 0 baud. if the ptc3 pin is at logic 0 during reset, the monitor baud rate is 9600. when the cgm output, cgmout, is driven by the pll, the baud rate is determined by the mul[7: 4] bits in the pll pr ogramming register (ppg). (see section 9. clock g enerator module (cgm) .) table 10-8. run (run u ser program) command description executes rti instruction operand none data returned none opcode $28 command sequence run run echo sent to monitor table 10-9. monitor baud rate selection monitor baud rate vco frequency multiplier (n) 123456 4.9152 mhz 4800 9600 14,400 19,200 24,000 28,800 4.194 mhz 4096 8192 12,288 16,384 20,480 24,576
monitor rom (mon) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 167 10.5 security a security feature discourages unaut horized reading of flash locations while in monitor mode. the host can bypass the securi ty feature at monitor mode entry by sending eight security bytes that match the bytes at locations $fff6?$fffd. locati ons $fff6?$fffd contain user- defined data. note: do not leave locati ons $fff6?$fffd blank . for security reasons, program locations $fff6?$fffd even if they are not used for vectors. during monitor mode entry, the mcu waits after the power-on reset for the host to send th e eight security bytes on pi n pta0. if the received bytes match those at location s $fff6?$fffd, the hos t bypasses the security feature and can read al l flash locations and execute code from flash. security remains bypa ssed until a power-on reset occurs. if the reset was not a power-on reset, security remains bypassed and security code entry is not required. (see figure 10-6 .) figure 10-6. monitor mode entry timing byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo pta0 rst v dd 4096 + 32 cgmxclk cycles 256 bus cycles (minimum) 1 4 1 1 2 1 break notes: 2 = data return delay, 2 bit times 4 = wait 1 bit time before sending next byte. 4 from host from mcu 1 = echo delay, 2 bit times
monitor rom (mon) technical data mc68hc908ab32 ? rev. 1.1 168 monitor rom (mon) freescale semiconductor upon power-on reset, if the receiv ed bytes of the se curity code do not match the data at loca tions $fff6?$fffd, the host fails to bypass the security feature. the mcu remain s in monitor mode, but reading a flash location returns an invalid val ue and trying to exec ute code from flash causes an illegal address reset. after receiving the eight security bytes from the host, the mc u transmits a br eak character, signifying that it is ready to receive a command. to determine whether the security c ode entered is correct, check to see if bit 6 of ram address $ 50 is set. if it is, then the correct security code has been entered and fl ash can be accessed. note: the mcu does not transmit a break character unti l after the host sends the eight security bits. if the host fails the securi ty bypass as described in 10.5 security , the mcu remains in monitor mode, but reading a flash lo cation returns an invalid value and trying to execut e code from flash causes an illegal address reset. the mcu monitor co mmands are still valid and user software can execute from ram. a bulk-erase operation is possible, erasing the entire flash memory, including the secu rity bytes at $fff6?$fffd. 10.6 extended security to further disable monitor mode functions, an extended security command keyword can be program med at flash locations $ffc0?$ffc7. the keyword is eight byte s long with a 7-byte ascii string and 1-byte $00 delimiter. the keyword for the mc68hc908ab32 mcu is "pswdopt" + $00. entry to monitor mode with ex tended security command keyword programmed, the mcu stops comm unicating with the host after transmitting a break character if the host fails the security bypass as described in 10.5 security . note: once the extended secu rity command keyword is programmed, the flash memory cannot be erased without a valid security code (matching $fff6?$fffd). t herefore, the exten ded security command keyword should not be programm ed during software development.
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module a (tima) 169 technical data ? mc68hc908ab32 section 11. timer interface module a (tima) 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 11.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 11.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 11.5.1 tima counter prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . .171 11.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 11.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 11.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 175 11.5.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .176 11.5.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 177 11.5.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 178 11.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 179 11.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 11.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 11.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 11.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 11.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 11.8 tima during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . . 182 11.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 11.9.1 tima clock pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 11.9.2 tima channel i/o pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 11.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 11.10.1 tima status an d control register . . . . . . . . . . . . . . . . . . . 184 11.10.2 tima counter registers. . . . . . . . . . . . . . . . . . . . . . . . . . .186 11.10.3 tima counter modulo registers . . . . . . . . . . . . . . . . . . . . 187 11.10.4 tima channel status and control registers . . . . . . . . . . . 188 11.10.5 tima channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . 192
timer interface module a (tima) technical data mc68hc908ab32 ? rev. 1.1 170 timer interface module a (tima) freescale semiconductor 11.2 introduction this section describes the timer inte rface module a (tima). the tima is a four-channel timer that provides a ti ming reference with input capture, output compare, and pulse-wid th-modulation functions. figure 11-1 is a block diagram of the tima. 11.3 features features of the tima include the following: four input capture/out put compare channels: ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse- width-modulation (pwm) signal generation programmable tima clock input: ? seven-frequency internal bus clock prescaler selection ? external tima clock inpu t (4mhz maximum frequency) free-running or modul o up-count operation toggle any channel pin on overflow tima counter stop and reset bits modular architecture expandable to eight channels
timer interface module a (tima) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module a (tima) 171 11.4 pin name conventions the tima share five i/o pi ns with port d, e, and f i/o pins. the full name of the tima i/o pin is listed in table 11-1 . the generic pi n name appear in the text that follows. 11.5 functional description figure 11-1 shows the structure of the tima. the central component of the tima is the 16-bit tima counte r that can operat e as a free-running counter or a modulo up-c ounter. the tima counter provides the timing reference for the input capture and output compare functions. the tima counter modulo registers, tamodh:t amodl, control the modulo value of the tima counter. software can re ad the tima counter value at any time without affectin g the counting sequence. the four tima channels are progr ammable independently as input capture or output compare channels. 11.5.1 tima counter prescaler the tima clock source can be one of the seven prescaler outputs or the tima clock pin, ptd6/taclk. the prescaler generat es seven clock rates from the internal bus clock. the prescaler se lect bits, ps[2:0], in the tima status and co ntrol register select the tima clock source. table 11-1. pin name conventions tima generic pin name s: full tima pin names: tac l k p t d 6 / tac l k tac h 0 p t e 2 / tac h 0 tac h 1 p t e 3 / tac h 1 tac h 2 p t f 0 / tac h 2 tac h 3 p t f 1 / tac h 3
timer interface module a (tima) technical data mc68hc908ab32 ? rev. 1.1 172 timer interface module a (tima) freescale semiconductor figure 11-1. tima block diagram prescaler prescaler select 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tach0h:tach0l ms0a els0b els0a tof toie 16-bit comparator 16-bit latch tach1h:tach1l 16-bit comparator 16-bit latch tach2h:tach2l 16-bit comparator 16-bit latch tach3h:tach3l channel 0 channel 1 channel 2 channel 3 tamodh:tamodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f els2b els2a tov2 ch2ie ch2max ch2f els3b els3a tov3 ch3ie ch3max ch3f ch0max ms0b ms2b 16-bit counter internal bus internal ms1a ms2a ms3a ptd6/taclk pte2/tach0 pte3/tach1 ptf0/tach2 ptf1/tach3 interrupt logic pte2 logic interrupt logic interrupt logic pte3 logic interrupt logic ptf0 logic interrupt logic ptf1 logic bus clock
timer interface module a (tima) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module a (tima) 173 addr.register name bit 7654321bit 0 $0020 timer a status and control register (tasc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0022 timer a counter register high (tacnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0023 timer a counter register low (tacntl) read: bit 7 654321bit 0 write: reset:00000000 $0024 timer a counter modulo register high (tamodh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $0025 timer a counter modulo register low (tamodl) read: bit 7654321bit 0 write: reset:11111111 $0026 timer a channel 0 status and control register (tasc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0027 timer a channel 0 register high (tach0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0028 timer a channel 0 register low (tach0l) read: bit 7654321bit 0 write: reset: indeterminate after reset $0029 timer a channel 1 status and control register (tasc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $002a timer a channel 1 register high (tach1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset = unimplemented figure 11-2. tima i/o register summary (sheet 1 of 2)
timer interface module a (tima) technical data mc68hc908ab32 ? rev. 1.1 174 timer interface module a (tima) freescale semiconductor 11.5.2 input capture with the input capture function, the tima can capture th e time at which an external event occurs . when an active edge o ccurs on the pin of an input capture channel, the tima la tches the contents of the tima counter into the tima channel regi sters, tachxh:tachxl. the polarity of the active edge is programmable. input captures can generate tima cpu interrupt requests. $002b timer a channel 1 register low (tach1l) read: bit 7654321bit 0 write: reset: indeterminate after reset $002c timer a channel 2 status and control register (tasc2) read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset:00000000 $002d timer a channel 2 register high (tach2h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $002e timer a channel 2 register low (tach2l) read: bit 7654321bit 0 write: reset: indeterminate after reset $002f timer a channel 3 status and control register (tasc3) read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset:00000000 $0030 timer a channel 3 register high (tach3h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0031 timer a channel 3 register low (tach3l) read: bit 7654321bit 0 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented figure 11-2. tima i/o register summary (sheet 2 of 2)
timer interface module a (tima) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module a (tima) 175 11.5.3 output compare with the output compare function, the tima can generate a periodic pulse with a progr ammable polarity, duration, and frequency. when the counter reaches the value in the r egisters of an output compare channel, the tima can se t, clear, or toggle the channel pin. output compares can generate tima cpu interrupt requests. 11.5.3.1 unbuffered output compare any output compare channel can generate unbuffered output compare pulses as described in 11.5.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the ol d value currently in th e tima channel registers. an unsynchronized write to the tima channel registers to change an output compare value could cause incorrect operati on for up to two counter overflow periods. for exampl e, writing a new value before the counter reaches the old value but after the c ounter reaches the new value prevents any compare during that counter overflow period. also, using a tima overflow interrupt rout ine to write a new , smaller output compare value may caus e the compare to be missed. the tima may pass the new value bef ore it is written. use the following methods to synch ronize unbuffered changes in the output compare va lue on channel x: when changing to a smaller va lue, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse . the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger out put compare value, enable channel x tima overflow interrupts and write the new value in the tima overflow interrupt routin e. the tima overflow interrupt occurs at the end of the current counter ove rflow period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) coul d cause two output compares to occur in the same counter overflow period.
timer interface module a (tima) technical data mc68hc908ab32 ? rev. 1.1 176 timer interface module a (tima) freescale semiconductor 11.5.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appe ars on the pte2/tach 0 pin. the tima channel registers of th e linked pair alternatel y control the output. setting the ms0b bit in tima channe l 0 status and control register (tasc0) links channel 0 and channel 1. the output compare value in the tima channel 0 regist ers initially controls the output on the pte2/tach0 pin. writing to the ti ma channel 1 registers enables the tima channel 1 registers to synchr onously control the output after the tima overflows. at each subseque nt overflow, the tima channel registers (0 or 1) that control the output are t he ones written to last. tasc0 controls and monitors the buf fered output compar e function, and tima channel 1 status and control regi ster (tasc1) is unused. while the ms0b bit is set, the channel 1 pin, pte3/tach1, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered output compare channel whose output appe ars on the ptf0/tach 2 pin. the tima channel registers of th e linked pair alternatel y control the output. setting the ms2b bit in tima channe l 2 status and control register (tasc2) links channel 2 and channel 3. the output compare value in the tima channel 2 regist ers initially controls the output on the ptf0/tach2 pin. writin g to the tima channel 3 registers enables the tima channel 3 registers to synchr onously control the output after the tima overflows. at each subseque nt overflow, the tima channel registers (2 or 3) that control the output are t he ones written to last. tasc2 controls and monitors the buf fered output compar e function, and tima channel 3 status and control regi ster (tasc3) is unused. while the ms2b bit is set, the channel 3 pin, ptf1/tach3, is available as a general-purpose i/o pin. note: in buffered output compare operati on, do not write new output compare values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered output compares.
timer interface module a (tima) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module a (tima) 177 11.5.4 pulse width modulation (pwm) by using the toggle-on-overflow f eature with an output compare channel, the tima can generate a pwm signal. the value in the tima counter modulo registers determi nes the period of th e pwm signal. the channel pin toggles when the counter reaches the value in the tima counter modulo registers. the time between ov erflows is the period of the pwm signal. as figure 11-3 shows, the output compare value in the tima channel registers determines t he pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the tima to clear the channel pin on output compare if the state of the pwm pulse is logic one. program the tima to set t he pin if the state of the pwm pulse is logic zero. figure 11-3pwm period and pulse width the value in the tima counter m odulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is va riable in 256 in crements. writing $00ff (255) to the tima counter modulo regi sters produces a pwm period of 256 times the in ternal bus clock period if the prescaler select value is $000. see 11.10.1 tima status and control register . the value in the tima channel regist ers determines the pulse width of the pwm output. the puls e width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tima channel registers produces a duty cycl e of 128/256 or 50%. tachx period pulse width overflow overflow overflow output compare output compare output compare
timer interface module a (tima) technical data mc68hc908ab32 ? rev. 1.1 178 timer interface module a (tima) freescale semiconductor 11.5.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 11.5.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currentl y in the tima channel registers. an unsynchronized write to the tima channel registers to change a pulse width value coul d cause incorrect operat ion for up to two pwm periods. for example, writing a ne w value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a ti ma overflow interrupt routine to write a new, smaller pulse width val ue may cause the compare to be missed. the tima may pass the new valu e before it is written. use the following methods to synch ronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pu lse. the interrupt routi ne has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable channel x tima overflow interrupts and write the new value in the tima overflow interrupt routine. the tima overflow interrupt occurs at the end of the current pwm period. writin g a larger value in an output compare interrupt routine (at t he end of the curr ent pulse) could cause two output compares to occur in the same pwm period. note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare also can cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value.
timer interface module a (tima) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module a (tima) 179 11.5.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the pte2 /tach0 pin. the tima channel registers of the linked pair alternately contro l the pulse width of the output. setting the ms0b bit in tima channe l 0 status and control register (tasc0) links channel 0 and channel 1. the tima channel 0 registers initially control the pulse width on the pte2/tach0 pin. writing to the tima channel 1 regist ers enables the tima channel 1 regi sters to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tima channel registers (0 or 1) that control the pul se width are the ones written to last. tasc0 controls and monitors the buffer ed pwm function, and tima channel 1 status and control register (tasc1) is unused. while the ms0b bit is set, the channel 1 pin, pte3/tach1, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered pwm channel whose output appears on the ptf0/tach2 pin. the tima channel registers of the linked pair alternately contro l the pulse width of the output. setting the ms2b bit in tima channe l 2 status and control register (tasc2) links channel 2 and channel 3. the tima channel 2 registers initially control the pulse width on the ptf0/tach2 pin. writing to the tima channel 3 regist ers enables the tima channel 3 regi sters to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tima channel registers (2 or 3) that control the pul se width are the ones written to last. tasc2 controls and monitors the buffer ed pwm function, and tima channel 3 status and control register (tasc3) is unused. while the ms2b bit is set, the channel 3 pin, ptf1/ tach3, is available as a general-purpose i/o pin. note: in buffered pwm signal gener ation, do not write new pulse width values to the currently active channel registers. writi ng to the acti ve channel registers is the same as gen erating unbuffe red pwm signals.
timer interface module a (tima) technical data mc68hc908ab32 ? rev. 1.1 180 timer interface module a (tima) freescale semiconductor 11.5.4.3 pwm initialization to ensure correct operation when gen erating unbuffered or buffered pwm signals, use the follow ing initializat ion procedure: 1. in the tima status and control register (tasc): a. stop the tima counter by sett ing the tima stop bit, tstop. b. reset the tima counter by sett ing the tima reset bit, trst. 2. in the tima counter modulo r egisters (tamodh:tamodl), write the value for the required pwm period. 3. in the tima channel x registers (tachxh :tachxl), write the value for the requ ired pulse width. 4. in tima channel x status and contro l register (tascx): a. write 0:1 (for unbuffered outp ut compare or pwm signals) or 1:0 (for buffered output com pare or pwm si gnals) to the mode select bits, msxb:msxa. see table 11-3 . a. write 1 to the toggle- on-overflow bit, tovx. b. write 1:0 (to clear output on co mpare) or 1:1 (to set output on compare) to the edge/level se lect bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pul se width level. see table 11-3 . note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare can also cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tima stat us control register (tasc) , clear the ti ma stop bit, tstop. setting ms0b links chann els 0 and 1 and configur es them for buffered pwm operation. the tima channel 0 registers (tach0h:tach0l) initially control the buffered pwm output. tima channel 0 status and control register 0 (tasc0) controls and monitors the pwm signal from the linked channels. ms0b ta kes priority over ms0a.
timer interface module a (tima) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module a (tima) 181 setting ms2b links chann els 2 and 3 and configur es them for buffered pwm operation. the tima channel 2 registers (tach2h:tach2l) initially control the pwm output. ti ma channel 2 stat us and control register (tasc2) contro ls and monitors the pwm signal from the linked channels. ms2b takes pr iority over ms2a. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tima overflows. subsequen t output compares try to force the output to a state it is already in and have no effect. the resu lt is a 0% duty cycle output. setting the channel x maximum dut y cycle bit (chxm ax) and clearing the tovx bit generates a 100% duty cycle output. see 11.10.4 tima channel status and c ontrol registers . 11.6 interrupts the following tima sources can generate interrupt requests: tima overflow flag (tof) ? the to f bit is set when the tima counter value rolls over to $0000 after matching t he value in the tima counter modulo registers. the tima overflow interrupt enable bit, toie, enables tima overflow cpu interrupt requests. tof and toie are in the tima status a nd control register. tima channel flags (ch3f?ch0f) ? the chxf bit is set when an input capture or output compar e occurs on channel x. channel x tim cpu interrupt requests ar e controlled by the channel x interrupt enable bit, chxie. c hannel x tim cpu interrupt requests are enabled when chxi e= 1. chxf and chxie are in the tima channel x status and control register. 11.7 low-power modes the wait and stop in structions puts the mcu in low-power- consumption standby modes.
timer interface module a (tima) technical data mc68hc908ab32 ? rev. 1.1 182 timer interface module a (tima) freescale semiconductor 11.7.1 wait mode the tima remains active af ter the execution of a wait instruction. in wait mode the tima registers ar e not accessible by the cpu. any enabled cpu interrupt reque st from the tima can bring the mcu out of wait mode. if tima functions are not requir ed during wait mode, reduce power consumption by stoppi ng the tima before ex ecuting the wait instruction. 11.7.2 stop mode the tima is inactive af ter the execution of a stop instruction. the stop instruction do es not affect register cond itions or the state of the tima counter. tima oper ation resumes when t he mcu exit stop mode after an external interrupt. 11.8 tima during break interrupts a break interrupt stops the tima counter. the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the sim break flag contro l register (sbfcr) enabl es software to clear status bits during the break state. see 8.8.3 sim break flag control register . to allow software to clear status bi ts during a break interrupt, write a logic one to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits dur ing the break state, writ e a logic zero to the bcfe bit. with bcfe at logic zero (its default state), software can read and write i/o registers during the br eak state without affecting status bits. some status bits have a two- step read/write cleari ng procedure. if software does the first step on such a bit before the brea k, the bit cannot change during the break stat e as long as bcfe is at logic zero. after the break, doing the second step clears the status bit.
timer interface module a (tima) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module a (tima) 183 11.9 i/o signals ports e and f each share two pins with the tima and port d shares one. ptd6/taclk is an external clock input to the tima prescaler. the four tima channel i/o pins are pte2 /tach0, pte3/tach1, ptf0/tach2, and ptf1/tach3. 11.9.1 tima clock pin ptd6/taclk is an external clock inpu t that can be the clock source for the tima counter instead of the presca led internal bus clock. select the ptd6/taclk input by writing logic 1s to the three prescaler select bits, ps[2:0]. see 11.10.1 tima status and control register . the minimum taclk pulse width, taclk lmin or taclk hmin , is: the maximum tacl k frequency is: bus frequency 2 ptd6/taclk is available as a gener al-purpose i/o pi n when not used as the tima clock input . when the ptd6/taclk pin is the tima clock input, it is an input regardless of the state of the ddrd6 bit in data direction register d. 11.9.2 tima channel i/o pins each channel i/o pin is progr ammable independently as an input capture pin or an output compar e pin. ptf0/tach2 and pte3/tach1 can be configured as buffered output compare or buffered pwm pins. 1 bus frequency ------------------ ------------------- t su +
timer interface module a (tima) technical data mc68hc908ab32 ? rev. 1.1 184 timer interface module a (tima) freescale semiconductor 11.10 i/o registers the following i/o registers control and monitor operation of the tima: tima status and cont rol register (tasc) tima counter regist ers (tacnth:tacntl) tima counter modulo regi sters (tamodh:tamodl) tima channel status and contro l registers (tasc0, tasc1, tasc2, and tasc3) tima channel registers (ta ch0h:tach0l, tach1h:tach1l, tach2h:tach2l, and tach3h:tach3l) 11.10.1 tima status and control register the tima status and control r egister does the following: enables tima overflow interrupts flags tima overflows stops the tima counter resets the tima counter prescales the tima counter clock address: $0020 bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 00100000 = unimplemented figure 11-4. tima status and control register (tasc)
timer interface module a (tima) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module a (tima) 185 tof ? tima overflow flag bit this read/write flag is set when the tima counter resets to $0000 after reaching the modulo value program med in the tima counter modulo registers. clear tof by reading the tima status and control register when tof is set and then wr iting a logic zero to tof. if another tima overflow occurs before the clear ing sequence is complete, then writing logic zero to tof has no effect. ther efore, a tof interrupt request cannot be lost du e to inadvertent clea ring of tof. reset clears the tof bit. writing a l ogic one to tof has no effect. 1 = tima counter ha s reached modulo value 0 = tima counter has not reached modulo value toie ? tima overflow interrupt enable bit this read/write bit enables tima overflow interr upts when the tof bit becomes set. reset cl ears the toie bit. 1 = tima overflow interrupts enabled 0 = tima overflow interrupts disabled tstop ? tima stop bit this read/write bit stop s the tima counter. counting resumes when tstop is cleared. reset sets t he tstop bit, stopping the tima counter until software clears the tstop bit. 1 = tima counter stopped 0 = tima counter active note: do not set the tstop bit before enter ing wait mode if the tima is required to exit wait mode. trst ? tima reset bit setting this write-only bit resets the tima counte r and the tima prescaler. setting trst has no ef fect on any other registers. counting resumes from $0000 . trst is cleared automatically after the tima counter is reset and alwa ys reads as logic zero. reset clears the trst bit. 1 = prescaler and tima counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the tima counter at a value of $0000.
timer interface module a (tima) technical data mc68hc908ab32 ? rev. 1.1 186 timer interface module a (tima) freescale semiconductor ps[2:0] ? prescaler select bits these read/write bits select either the ptd6/taclk pin or one of the seven prescaler outputs as the input to the tima counter as table 11-2 shows. reset clear s the ps[2:0] bits. 11.10.2 tima counter registers the two read-only tima counter regist ers contain the high and low bytes of the value in the tima counter . reading the high byte (tacnth) latches the contents of the low byte (tacntl) into a buffer. subsequent reads of tacnth do not affect the latched tacntl value until tacntl is read. reset clears the tima counter registers. setting the tima reset bit (trst) also clears t he tima counter registers. note: if you read tacnth during a break in terrupt, be sure to unlatch tacntl by reading tacntl before exiting the break interrupt. otherwise, tacntl retains the value latched during the break. table 11-2. pres caler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock 1 0 0 1 internal bus clock 2 0 1 0 internal bus clock 4 0 1 1 internal bus clock 8 1 0 0 internal bus clock 16 1 0 1 internal bus clock 32 1 1 0 internal bus clock 64 111 ptd6/taclk address: $0022 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 = unimplemented figure 11-5. tima counter register high (tacnth)
timer interface module a (tima) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module a (tima) 187 11.10.3 tima counter modulo registers the read/write tima modulo registers contain the modulo value for the tima counter. when the tima counter reaches the m odulo value, the overflow flag (tof) bec omes set, an d the tima counter resumes counting from $0000 at the next cl ock. writing to the high byte (tamodh) inhibits the to f bit and overflow interr upts until the low byte (tamodl) is written. reset sets the tima counter modulo registers. note: reset the tima counter before wr iting to the tima counter modulo registers. address: $0023 bit 7654321bit 0 read: bit 7 654321bit 0 write: reset:00000000 = unimplemented figure 11-6. ti ma counter regi ster low (tacntl) address: $0024 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 figure 11-7. tima counter mo dulo register high (tamodh) address: $0025 bit 7654321bit 0 read: bit 7654321bit 0 write: reset:11111111 figure 11-8. tima counter modulo register low (tamodl)
timer interface module a (tima) technical data mc68hc908ab32 ? rev. 1.1 188 timer interface module a (tima) freescale semiconductor 11.10.4 tima channel status and control registers each of the tima channel status and control registers does the following: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or t oggling output on output compare selects rising edge, fall ing edge, or any edge as the active input capture trigger selects output toggl ing on tima overflow selects 100% pwm duty cycle selects buffered or unbuffer ed output compare/pwm operation address: $0026 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 figure 11-9. tima channel 0 stat us and control register (tasc0) address: $0029 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 figure 11-10. tima c hannel 1 status and contro l register (tasc1)
timer interface module a (tima) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module a (tima) 189 chxf ? chann el x flag bit when channel x is an inpu t capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the tima counter registers matche s the value in the ti ma channel x registers. when tim cpu interrupt requests ar e enabled (chxie = 1), clear chxf by reading tima channel x status an d control register with chxf set and then writing a logic zero to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic zero to chxf has no effe ct. therefore, an interrupt request cannot be lost due to inadver tent clearing of chxf. reset clears the chxf bit. writing a logic one to chxf has no effect. 1 = input capture or out put compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x in terrupt enable bit this read/write bit enables tima cpu in terrupts on channel x. reset clears the chxie bit. 1 = channel x cpu inte rrupt requests enabled 0 = channel x cpu interr upt requests disabled address: $002c bit 7654321bit 0 read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset:00000000 figure 11-11. tima c hannel 2 status and contro l register (tasc2) address: $002f bit 7654321bit 0 read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset:00000000 figure 11-12. tima c hannel 3 status and contro l register (tasc3)
timer interface module a (tima) technical data mc68hc908ab32 ? rev. 1.1 190 timer interface module a (tima) freescale semiconductor msxb ? mode select bit b this read/write bit sele cts buffered output co mpare/pwm operation. msxb exists only in the tima c hannel 0 and tima ch annel 2 status and control registers. setting ms0b disables the channel 1 status and control register and reverts tch1b to general-purpose i/o. setting ms2b disables the channel 3 status and control register and reverts tch3b to general-purpose i/o. reset clears the msxb bit. 1 = buffered output com pare/pwm operation enabled 0 = buffered output compar e/pwm operation disabled msxa ? mode select bit a when elsxb:a 00, this read/write bit se lects either input capture operation or unbuffered outp ut compare/pwm operation. see table 11-3 . 1 = unbuffered output compare/pwm operation 0 = input capt ure operation when elsxb:a = 00, this read/write bit selects the in itial output level of the tbchx pin. see table 11-3 . reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bi ts in the tima status and control register (tasc). elsxb and elsxa ? edge/level select bits when channel x is an i nput capture channel, th ese read/write bits control the active edge- sensing logic on channel x. when channel x is an output co mpare channel, elsxb and elsxa control the channel x output beh avior when an output compare occurs. when elsxb and elsxa are both cl ear, channel x is not connected to the port i/o, and pi n tachx is available as a general-purpose i/o pin. table 11-3 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits.
timer interface module a (tima) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module a (tima) 191 note: before enabling a tima channel register for input capture operation, make sure that the tachx pin is stable for at least two bus clocks. tovx ? toggle-on-overflow bit when channel x is an output compar e channel, this read/write bit controls the behavior of the channel x output when the tima counter overflows. when channel x is an i nput capture channel, tovx has no effect. reset clear s the tovx bit. 1 = channel x pin toggles on tima counter overflow. 0 = channel x pin does not toggl e on tima counter overflow. note: when tovx is set, a tima counter overflow takes precedence over a channel x output compare if bot h occur at the same time. chxmax ? channel x ma ximum duty cycle bit when the tovx bit is at logic zero, setting the chxmax bit forces the duty cycle of buffered and unbuffe red pwm signals to 100%. as figure 11-13 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. table 11-3. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin under port control; initial output level high x1 0 0 pin under port control; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 01 0 1 output compare or pwm toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1x 0 1buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare
timer interface module a (tima) technical data mc68hc908ab32 ? rev. 1.1 192 timer interface module a (tima) freescale semiconductor figure 11-13. chxmax latency 11.10.5 tima channel registers these read/write registers contain t he captured tima c ounter value of the input capture functi on or the output compar e value of the output compare function. the stat e of the tima channel registers after reset is unknown. in input capture mode (m sxb:msxa = 0:0), reading the high byte of the tima channel x registers (tachxh) inhibits input captures until the low byte (tachxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the tima channel x regist ers (tachxh) inhibits output compares until the low byte (tachxl) is written. output overflow tachx period chxmax overflow overflow overflow overflow compare output compare output compare output compare address: $0027 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 11-14. tima channel 0 register high (tach0h) address: $0028 bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 11-15. tima channel 0 register low (tach0l)
timer interface module a (tima) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module a (tima) 193 address: $002a bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 11-16. tima channel 1 register high (tach1h) address: $002b bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 11-17. tima channel 1 register low (tach1l) address: $002d bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 11-18. tima channel 2 register high (tach2h) address: $002e bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 11-19. tima channel 2 register low (tach2l)
timer interface module a (tima) technical data mc68hc908ab32 ? rev. 1.1 194 timer interface module a (tima) freescale semiconductor address: $0030 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 11-20. tima channel 3 register high (tach3h) address: $0031 bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 11-21. tima channel 3 register low (tach3l)
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module b (timb) 195 technical data ? mc68hc908ab32 section 12. timer interface module b (timb) 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 12.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 12.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 12.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 12.5.1 timb counter prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . .197 12.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 12.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 12.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 201 12.5.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .202 12.5.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 203 12.5.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 204 12.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 205 12.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 12.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 12.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 12.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 12.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 12.8 timb during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . . 208 12.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 12.9.1 timb clock pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 12.9.2 timb channel i/o pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 12.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 12.10.1 timb status an d control register . . . . . . . . . . . . . . . . . . . 210 12.10.2 timb counter registers. . . . . . . . . . . . . . . . . . . . . . . . . . .212 12.10.3 timb counter modulo registers . . . . . . . . . . . . . . . . . . . . 213 12.10.4 timb channel status and control registers . . . . . . . . . . . 214 12.10.5 timb channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . 218
timer interface module b (timb) technical data mc68hc908ab32 ? rev. 1.1 196 timer interface module b (timb) freescale semiconductor 12.2 introduction this section describes the timer inte rface module a (timb). the timb is a four-channel timer that provides a ti ming reference with input capture, output compare, and pulse-wid th-modulation functions. figure 12-1 is a block diagram of the timb. 12.3 features features of the timb include the following: four input capture/out put compare channels: ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse- width-modulation (pwm) signal generation programmable timb clock input: ? seven-frequency internal bus clock prescaler selection ? external timb clock inpu t (4mhz maximum frequency) free-running or modul o up-count operation toggle any channel pin on overflow timb counter stop and reset bits modular architecture expandable to eight channels
timer interface module b (timb) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module b (timb) 197 12.4 pin name conventions the timb share five i/o pins with po rt d and f i/o pins. the full name of the timb i/o pin is listed in table 12-1 . the generic pi n name appear in the text that follows. 12.5 functional description figure 12-1 shows the structure of the timb. the central component of the timb is the 16-bit timb counte r that can operat e as a free-running counter or a modulo up-c ounter. the timb counter provides the timing reference for the input capture and output compare functions. the timb counter modulo registers, tbmodh:t bmodl, control the modulo value of the timb counter. software can re ad the timb counter value at any time without affectin g the counting sequence. the four timb channels are progr ammable independently as input capture or output compare channels. 12.5.1 timb counter prescaler the timb clock source can be one of the seven prescaler outputs or the timb clock pin, ptd4/tbclk. the prescaler generat es seven clock rates from the internal bus clock. the prescaler se lect bits, ps[2:0], in the timb status and co ntrol register select the timb clock source. table 12-1. pin name conventions timb generic pin name s: full timb pin names: tbclk ptd4/tbclk tbch0 ptf4/tbch0 tbch1 ptf5/tbch1 tbch2 ptf2/tbch2 tbch3 ptf3/tbch3
timer interface module b (timb) technical data mc68hc908ab32 ? rev. 1.1 198 timer interface module b (timb) freescale semiconductor figure 12-1. timb block diagram prescaler prescaler select 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tbch0h:tbch0l ms0a els0b els0a tof toie 16-bit comparator 16-bit latch tbch1h:tbch1l 16-bit comparator 16-bit latch tbch2h:tbch2l 16-bit comparator 16-bit latch tbch3h:tbch3l channel 0 channel 1 channel 2 channel 3 tbmodh:tbmodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f els2b els2a tov2 ch2ie ch2max ch2f els3b els3a tov3 ch3ie ch3max ch3f ch0max ms0b ms2b 16-bit counter internal bus internal ms1a ms2a ms3a ptd4/tbclk ptf4/tbch0 ptf5/tbch1 ptf2/tbch2 t ptf3/tbch3 interrupt logic ptf4 logic interrupt logic interrupt logic ptf5 logic interrupt logic ptf2 logic interrupt logic ptf3 logic bus clock
timer interface module b (timb) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module b (timb) 199 addr.register name bit 7654321bit 0 $0040 timer b status and control register (tbsc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $0041 timer b counter register high (tbcnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $0042 timer b counter register low (tbcntl) read: bit 7 654321bit 0 write: reset:00000000 $0043 timer b counter modulo register high (tbmodh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $0044 timer b counter modulo register low (tbmodl) read: bit 7654321bit 0 write: reset:11111111 $0045 timer b channel 0 status and control register (tbsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0046 timer b channel 0 register high (tbch0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0047 timer b channel 0 register low (tbch0l) read: bit 7654321bit 0 write: reset: indeterminate after reset $0048 timer b channel 1 status and control register (tbsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 $0049 timer b channel 1 register high (tbch1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset = unimplemented figure 12-2. timb i/o register summary (sheet 1 of 2)
timer interface module b (timb) technical data mc68hc908ab32 ? rev. 1.1 200 timer interface module b (timb) freescale semiconductor 12.5.2 input capture with the input capture function, the timb can capture th e time at which an external event occurs . when an active edge o ccurs on the pin of an input capture channel, the timb la tches the contents of the timb counter into the timb channel regi sters, tbchxh:tbchxl. the polarity of the active edge is programmable. input captures can generate timb cpu interrupt requests. $004a timer b channel 1 register low (tbch1l) read: bit 7654321bit 0 write: reset: indeterminate after reset $0032 timer b channel 2 status and control register (tbsc2) read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset:00000000 $0033 timer b channel 2 register high (tbch2h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0034 timer b channel 2 register low (tbch2l) read: bit 7654321bit 0 write: reset: indeterminate after reset $0035 timer b channel 3 status and control register (tbsc3) read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset:00000000 $0036 timer b channel 3 register high (tbch3h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset $0037 timer b channel 3 register low (tbch3l) read: bit 7654321bit 0 write: reset: indeterminate after reset addr.register name bit 7654321bit 0 = unimplemented figure 12-2. timb i/o register summary (sheet 2 of 2)
timer interface module b (timb) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module b (timb) 201 12.5.3 output compare with the output compare function, the timb can generate a periodic pulse with a progr ammable polarity, duration, and frequency. when the counter reaches the value in the r egisters of an output compare channel, the timb can se t, clear, or toggle the channel pin. output compares can generate timb cpu interrupt requests. 12.5.3.1 unbuffered output compare any output compare channel can generate unbuffered output compare pulses as described in 12.5.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the ol d value currently in th e timb channel registers. an unsynchronized write to the timb channel registers to change an output compare value could cause incorrect operati on for up to two counter overflow periods. for exampl e, writing a new value before the counter reaches the old value but after the c ounter reaches the new value prevents any compare during that counter overflow period. also, using a timb overflow interrupt rout ine to write a new , smaller output compare value may caus e the compare to be missed. the timb may pass the new value bef ore it is written. use the following methods to synch ronize unbuffered changes in the output compare va lue on channel x: when changing to a smaller va lue, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse . the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger out put compare value, enable channel x timb overflow interrupts and write the new value in the timb overflow interrupt routin e. the timb overflow interrupt occurs at the end of the current counter ove rflow period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) coul d cause two output compares to occur in the same counter overflow period.
timer interface module b (timb) technical data mc68hc908ab32 ? rev. 1.1 202 timer interface module b (timb) freescale semiconductor 12.5.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appe ars on the ptf4/tbch 0 pin. the timb channel registers of th e linked pair alternatel y control the output. setting the ms0b bit in timb channe l 0 status and control register (tbsc0) links channel 0 and channel 1. the output compare value in the timb channel 0 regist ers initially controls the output on the ptf4/tbch0 pin. writin g to the timb channel 1 registers enables the timb channel 1 registers to synchr onously control the output after the timb overflows. at each subseque nt overflow, the timb channel registers (0 or 1) that control the output are t he ones written to last. tbsc0 controls and monitors the buf fered output compar e function, and timb channel 1 status and control regi ster (tbsc1) is unused. while the ms0b bit is set, the channel 1 pin, ptf5/tbch1, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered output compare channel whose output appe ars on the ptf2/tbch 2 pin. the timb channel registers of th e linked pair alternatel y control the output. setting the ms2b bit in timb channe l 2 status and control register (tbsc2) links channel 2 and channel 3. the output compare value in the timb channel 2 regist ers initially controls the output on the ptf2/tbch2 pin. writin g to the timb channel 3 registers enables the timb channel 3 registers to synchr onously control the output after the timb overflows. at each subseque nt overflow, the timb channel registers (2 or 3) that control the output are t he ones written to last. tbsc2 controls and monitors the buf fered output compar e function, and timb channel 3 status and control regi ster (tbsc3) is unused. while the ms2b bit is set, the channel 3 pin, ptf3/tbch3, is available as a general-purpose i/o pin. note: in buffered output compare operati on, do not write new output compare values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered output compares.
timer interface module b (timb) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module b (timb) 203 12.5.4 pulse width modulation (pwm) by using the toggle-on-overflow f eature with an output compare channel, the timb can generate a pwm signal. the value in the timb counter modulo registers determi nes the period of th e pwm signal. the channel pin toggles when the counter reaches the value in the timb counter modulo registers. the time between ov erflows is the period of the pwm signal. as figure 12-3 shows, the output compare value in the timb channel registers determines t he pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the timb to clear the channel pin on output compare if the state of the pwm pulse is logic one. program the timb to set t he pin if the state of the pwm pulse is logic zero. figure 12-3pwm period and pulse width the value in the timb counter m odulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is va riable in 256 in crements. writing $00ff (255) to the timb counter modulo regi sters produces a pwm period of 256 times the in ternal bus clock period if the prescaler select value is $000. see 12.10.1 timb status and control register . the value in the timb channel regist ers determines the pulse width of the pwm output. the puls e width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the timb channel registers produces a duty cycl e of 128/256 or 50%. tbchx period pulse width overflow overflow overflow output compare output compare output compare
timer interface module b (timb) technical data mc68hc908ab32 ? rev. 1.1 204 timer interface module b (timb) freescale semiconductor 12.5.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 12.5.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currentl y in the timb channel registers. an unsynchronized write to the timb channel registers to change a pulse width value coul d cause incorrect operat ion for up to two pwm periods. for example, writing a ne w value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a ti mb overflow interrupt routine to write a new, smaller pulse width val ue may cause the compare to be missed. the timb may pass the new valu e before it is written. use the following methods to synch ronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pu lse. the interrupt routi ne has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable channel x timb overflow interrupts and write the new value in the timb overflow interrupt routine. the timb overflow interrupt occurs at the end of the current pwm period. writin g a larger value in an output compare interrupt routine (at t he end of the curr ent pulse) could cause two output compares to occur in the same pwm period. note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare also can cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value.
timer interface module b (timb) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module b (timb) 205 12.5.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the ptf4/tbch0 pin. the timb channel registers of the linked pair alternately contro l the pulse width of the output. setting the ms0b bit in timb channe l 0 status and control register (tbsc0) links channel 0 and channel 1. the timb channel 0 registers initially control the pulse width on the ptf4/tbch0 pin. writing to the timb channel 1 regist ers enables the timb channel 1 regi sters to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the timb channel registers (0 or 1) that control the pul se width are the ones written to last. tbsc0 controls and monitors the buffer ed pwm function, and timb channel 1 status and control register (tbsc1) is unused. while the ms0b bit is set, the channel 1 pin, ptf5/ tbch1, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered pwm channel whose output appears on the ptf2/tbch2 pin. the timb channel registers of the linked pair alternately contro l the pulse width of the output. setting the ms2b bit in timb channe l 2 status and control register (tbsc2) links channel 2 and channel 3. the timb channel 2 registers initially control the pulse width on the ptf2/tbch2 pin. writing to the timb channel 3 regist ers enables the timb channel 3 regi sters to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the timb channel registers (2 or 3) that control the pul se width are the ones written to last. tbsc2 controls and monitors the buffer ed pwm function, and timb channel 3 status and control register (tbsc3) is unused. while the ms2b bit is set, the channel 3 pin, ptf3/ tbch3, is available as a general-purpose i/o pin. note: in buffered pwm signal gener ation, do not write new pulse width values to the currently active channel registers. writi ng to the acti ve channel registers is the same as gen erating unbuffe red pwm signals.
timer interface module b (timb) technical data mc68hc908ab32 ? rev. 1.1 206 timer interface module b (timb) freescale semiconductor 12.5.4.3 pwm initialization to ensure correct operation when gen erating unbuffered or buffered pwm signals, use the follow ing initializat ion procedure: 1. in the timb status and control register (tbsc): a. stop the timb counter by sett ing the timb stop bit, tstop. b. reset the timb counter by sett ing the timb reset bit, trst. 2. in the timb counter modulo r egisters (tbmodh:tbmodl), write the value for the required pwm period. 3. in the timb channel x registers (tbchxh :tbchxl), write the value for the requ ired pulse width. 4. in timb channel x status and contro l register (tbscx): a. write 0:1 (for unbuffered outp ut compare or pwm signals) or 1:0 (for buffered output com pare or pwm si gnals) to the mode select bits, msxb:msxa. see table 12-3 . a. write 1 to the toggle- on-overflow bit, tovx. b. write 1:0 (to clear output on co mpare) or 1:1 (to set output on compare) to the edge/level se lect bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pul se width level. see table 12-3 . note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare can also cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the timb stat us control register (tbsc) , clear the ti mb stop bit, tstop. setting ms0b links chann els 0 and 1 and configur es them for buffered pwm operation. the timb channel 0 registers (tbch0h:tbch0l) initially control the buffered pwm output. timb channel 0 status and control register (tbsc0) controls and monitors the pw m signal from the linked channels. ms0b take s priority over ms0a.
timer interface module b (timb) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module b (timb) 207 setting ms2b links chann els 2 and 3 and configur es them for buffered pwm operation. the timb channel 2 registers (tbch2h:tbch2l) initially control the pwm output. ti mb channel 2 stat us and control register (tbsc2) contro ls and monitors the pwm signal from the linked channels. ms2b takes pr iority over ms2a. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on timb overflows. subsequen t output compares try to force the output to a state it is already in and have no effect. the resu lt is a 0% duty cycle output. setting the channel x maximum dut y cycle bit (chxm ax) and clearing the tovx bit generates a 100% duty cycle output. see 12.10.4 timb channel status and c ontrol registers . 12.6 interrupts the following timb sources can generate interrupt requests: timb overflow flag (tof) ? the to f bit is set when the timb counter value rolls over to $0000 after matching t he value in the timb counter modulo registers. the timb overflow interrupt enable bit, toie, enables timb overflow cpu interrupt requests. tof and toie are in the timb status a nd control register. timb channel flags (ch3f?ch0f) ? the chxf bit is set when an input capture or output compar e occurs on channel x. channel x tim cpu interrupt requests ar e controlled by the channel x interrupt enable bit, chxie. c hannel x tim cpu interrupt requests are enabled when chxi e= 1. chxf and chxie are in the timb channel x status and control register. 12.7 low-power modes the wait and stop in structions puts the mcu in low-power- consumption standby modes.
timer interface module b (timb) technical data mc68hc908ab32 ? rev. 1.1 208 timer interface module b (timb) freescale semiconductor 12.7.1 wait mode the timb remains active af ter the execution of a wait instruction. in wait mode the timb registers ar e not accessible by the cpu. any enabled cpu interrupt reque st from the timb can bring the mcu out of wait mode. if timb functions are not requir ed during wait mode, reduce power consumption by stoppi ng the timb before ex ecuting the wait instruction. 12.7.2 stop mode the timb is inactive af ter the execution of a stop instruction. the stop instruction do es not affect register cond itions or the state of the timb counter. timb oper ation resumes when t he mcu exit stop mode after an external interrupt. 12.8 timb during break interrupts a break interrupt stops the timb counter. the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the sim break flag contro l register (sbfcr) enabl es software to clear status bits during the break state. see 8.8.3 sim break flag control register . to allow software to clear status bi ts during a break interrupt, write a logic one to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits dur ing the break state, writ e a logic zero to the bcfe bit. with bcfe at logic zero (its default state), software can read and write i/o registers during the br eak state without affecting status bits. some status bits have a two- step read/write cleari ng procedure. if software does the first step on such a bit before the brea k, the bit cannot change during the break stat e as long as bcfe is at logic zero. after the break, doing the second step clears the status bit.
timer interface module b (timb) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module b (timb) 209 12.9 i/o signals port f shares four pins with the timb and port d shares one. ptd4/tbclk is an external clock input to the timb prescaler. the four timb channel i/o pins are ptf4/ tbch0, ptf5/tbch1, ptf2/tbch2, and ptf3/tbch3. 12.9.1 timb clock pin ptd4/tbclk is an external clock inpu t that can be the clock source for the timb counter instead of the presca led internal bus clock. select the ptd4/tbclk input by writing logic 1s to the three prescaler select bits, ps[2:0]. see 12.10.1 timb status and control register . the minimum tbclk pulse width, tbclk lmin or tbclk hmin , is: the maximum tbcl k frequency is: bus frequency 2 ptd4/tbclk is available as a gener al-purpose i/o pi n when not used as the timb clock input . when the ptd4/tbclk pin is the timb clock input, it is an input regardless of the state of the ddrd6 bit in data direction register d. 12.9.2 timb channel i/o pins each channel i/o pin is progr ammable independently as an input capture pin or an output compare pin. ptf2/tbch2 and ptf5/tbch1 can be configured as buffered output compare or buffered pwm pins. 1 bus frequency ------------------ ------------------- t su +
timer interface module b (timb) technical data mc68hc908ab32 ? rev. 1.1 210 timer interface module b (timb) freescale semiconductor 12.10 i/o registers the following i/o registers control and monitor operation of the timb: timb status and cont rol register (tbsc) timb counter regist ers (tbcnth:tbcntl) timb counter modulo regi sters (tbmodh:tbmodl) timb channel status and contro l registers (tbsc0, tbsc1, tbsc2, and tbsc3) timb channel registers (tb ch0h:tbch0l, tbch1h:tbch1l, tbch2h:tbch2l, and tbch3h:tbch3l) 12.10.1 timb status and control register the timb status and control r egister does the following: enables timb overflow interrupts flags timb overflows stops the timb counter resets the timb counter prescales the timb counter clock address: $0040 bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 00100000 = unimplemented figure 12-4. timb status and control register (tbsc)
timer interface module b (timb) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module b (timb) 211 tof ? timb overflow flag bit this read/write flag is set when the timb counter resets to $0000 after reaching the modulo value program med in the timb counter modulo registers. clear tof by reading the timb status and control register when tof is set and then wr iting a logic zero to tof. if another timb overflow occurs before the clear ing sequence is complete, then writing logic zero to tof has no effect. ther efore, a tof interrupt request cannot be lost du e to inadvertent clea ring of tof. reset clears the tof bit. writing a l ogic one to tof has no effect. 1 = timb counter ha s reached modulo value 0 = timb counter has not reached modulo value toie ? timb overflow interrupt enable bit this read/write bit enables timb overflow interr upts when the tof bit becomes set. reset cl ears the toie bit. 1 = timb overflow interrupts enabled 0 = timb overflow interrupts disabled tstop ? timb stop bit this read/write bit stop s the timb counter. counting resumes when tstop is cleared. reset sets t he tstop bit, stopping the timb counter until software clears the tstop bit. 1 = timb counter stopped 0 = timb counter active note: do not set the tstop bit before enter ing wait mode if the timb is required to exit wait mode. trst ? timb reset bit setting this write-only bit resets the timb counte r and the timb prescaler. setting trst has no ef fect on any other registers. counting resumes from $0000 . trst is cleared automatically after the timb counter is reset and alwa ys reads as logic zero. reset clears the trst bit. 1 = prescaler and timb counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the timb counter at a value of $0000.
timer interface module b (timb) technical data mc68hc908ab32 ? rev. 1.1 212 timer interface module b (timb) freescale semiconductor ps[2:0] ? prescaler select bits these read/write bits select either the ptd4/tbclk pin or one of the seven prescaler outputs as the input to the timb counter as table 12-2 shows. reset clear s the ps[2:0] bits. 12.10.2 timb counter registers the two read-only timb counter regist ers contain the high and low bytes of the value in the timb counter . reading the high byte (tbcnth) latches the contents of the low byte (tbcntl) into a buffer. subsequent reads of tbcnth do not affect the latched tbcntl value until tbcntl is read. reset clears the timb counter registers. setting the timb reset bit (trst) also clears t he timb counter registers. note: if you read tbcnth during a break in terrupt, be sure to unlatch tbcntl by reading tbcntl before exiting the break interrupt. otherwise, tbcntl retains the value latched during the break. table 12-2. pres caler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock 1 0 0 1 internal bus clock 2 0 1 0 internal bus clock 4 0 1 1 internal bus clock 8 1 0 0 internal bus clock 16 1 0 1 internal bus clock 32 1 1 0 internal bus clock 64 111 ptd4/tbclk address: $0041 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 = unimplemented figure 12-5. timb counter register high (tbcnth)
timer interface module b (timb) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module b (timb) 213 12.10.3 timb counter modulo registers the read/write timb modulo registers contain the modulo value for the timb counter. when the timb counter reaches the m odulo value, the overflow flag (tof) bec omes set, an d the timb counter resumes counting from $0000 at the next cl ock. writing to the high byte (tbmodh) inhibits the to f bit and overflow interr upts until the low byte (tbmodl) is written. reset sets the timb counter modulo registers. note: reset the timb counter before wr iting to the timb counter modulo registers. address: $0042 bit 7654321bit 0 read: bit 7 654321bit 0 write: reset:00000000 = unimplemented figure 12-6. ti mb counter regi ster low (tbcntl) address: $0043 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 figure 12-7. timb counter mo dulo register high (tbmodh) address: $0044 bit 7654321bit 0 read: bit 7654321bit 0 write: reset:11111111 figure 12-8. timb counter modulo register low (tbmodl)
timer interface module b (timb) technical data mc68hc908ab32 ? rev. 1.1 214 timer interface module b (timb) freescale semiconductor 12.10.4 timb channel status and control registers each of the timb channel status and control registers does the following: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or t oggling output on output compare selects rising edge, fall ing edge, or any edge as the active input capture trigger selects output toggl ing on timb overflow selects 100% pwm duty cycle selects buffered or unbuffer ed output compare/pwm operation address: $0045 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 figure 12-9. timb channel 0 stat us and control register (tbsc0) address: $0048 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 figure 12-10. timb c hannel 1 status and contro l register (tbsc1)
timer interface module b (timb) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module b (timb) 215 chxf ? chann el x flag bit when channel x is an inpu t capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the timb counter registers matche s the value in the ti mb channel x registers. when tim cpu interrupt requests ar e enabled (chxie = 1), clear chxf by reading timb channel x status an d control register with chxf set and then writing a logic zero to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic zero to chxf has no effe ct. therefore, an interrupt request cannot be lost due to inadver tent clearing of chxf. reset clears the chxf bit. writing a logic one to chxf has no effect. 1 = input capture or out put compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x in terrupt enable bit this read/write bit enables timb cpu in terrupts on channel x. reset clears the chxie bit. 1 = channel x cpu inte rrupt requests enabled 0 = channel x cpu interr upt requests disabled address: $0032 bit 7654321bit 0 read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset:00000000 figure 12-11. timb c hannel 2 status and contro l register (tbsc2) address: $0035 bit 7654321bit 0 read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset:00000000 figure 12-12. timb c hannel 3 status and contro l register (tbsc3)
timer interface module b (timb) technical data mc68hc908ab32 ? rev. 1.1 216 timer interface module b (timb) freescale semiconductor msxb ? mode select bit b this read/write bit sele cts buffered output co mpare/pwm operation. msxb exists only in the timb c hannel 0 and timb ch annel 2 status and control registers. setting ms0b disables the channel 1 status and control register and reverts tch1b to general-purpose i/o. setting ms2b disables the channel 3 status and control register and reverts tch3b to general-purpose i/o. reset clears the msxb bit. 1 = buffered output com pare/pwm operation enabled 0 = buffered output compar e/pwm operation disabled msxa ? mode select bit a when elsxb:a 00, this read/write bit se lects either input capture operation or unbuffered output compare/pwm operation. see table 12-3 . 1 = unbuffered output compare/pwm operation 0 = input capt ure operation when elsxb:a = 00, this read/write bit selects the in itial output level of the tbchx pin. see table 12-3 . reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bi ts in the timb status and control register (tbsc). elsxb and elsxa ? edge/level select bits when channel x is an i nput capture channel, th ese read/write bits control the active edge- sensing logic on channel x. when channel x is an output co mpare channel, elsxb and elsxa control the channel x output beh avior when an output compare occurs. when elsxb and elsxa are both cl ear, channel x is not connected to the port i/o, and pi n tbchx is available as a general-purpose i/o pin. table 12-3 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits.
timer interface module b (timb) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module b (timb) 217 note: before enabling a timb channel register for input capture operation, make sure that the tbchx pin is stable for at least two bus clocks. tovx ? toggle-on-overflow bit when channel x is an output compar e channel, this read/write bit controls the behavior of the channel x output when the timb counter overflows. when channel x is an i nput capture channel, tovx has no effect. reset clear s the tovx bit. 1 = channel x pin toggles on timb counter overflow. 0 = channel x pin does not toggl e on timb counter overflow. note: when tovx is set, a timb counter overflow takes precedence over a channel x output compare if bot h occur at the same time. chxmax ? channel x ma ximum duty cycle bit when the tovx bit is at logic zero, setting the chxmax bit forces the duty cycle of buffered and unbuffe red pwm signals to 100%. as figure 12-13 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. table 12-3. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin under port control; initial output level high x1 0 0 pin under port control; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 01 0 1 output compare or pwm toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1x 0 1buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare
timer interface module b (timb) technical data mc68hc908ab32 ? rev. 1.1 218 timer interface module b (timb) freescale semiconductor figure 12-13. chxmax latency 12.10.5 timb channel registers these read/write registers contain t he captured timb c ounter value of the input capture functi on or the output compar e value of the output compare function. the stat e of the timb channel registers after reset is unknown. in input capture mode (m sxb:msxa = 0:0), reading the high byte of the timb channel x registers (tbchxh) inhibits input captures until the low byte (tbchxl) is read. in output compare mode (msxb:msxa 0:0), writing to the high byte of the timb channel x regist ers (tbchxh) inhibits output compares until the low byte (tbchxl) is written. output overflow tbchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare address: $0046 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 12-14. timb channel 0 register high (tbch0h) address: $0047 bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 12-15. timb channel 0 register low (tbch0l)
timer interface module b (timb) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor timer interface module b (timb) 219 address: $0049 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 12-16. timb channel 1 register high (tbch1h) address: $004a bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 12-17. timb channel 1 register low (tbch1l) address: $0033 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 12-18. timb channel 2 register high (tbch2h) address: $0034 bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 12-19. timb channel 2 register low (tbch2l)
timer interface module b (timb) technical data mc68hc908ab32 ? rev. 1.1 220 timer interface module b (timb) freescale semiconductor address: $0036 bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset figure 12-20. timb channel 3 register high (tbch3h) address: $0037 bit 7654321bit 0 read: bit 7654321bit 0 write: reset: indeterminate after reset figure 12-21. timb channel 3 register low (tbch3l)
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor programmable interrupt timer (pit) 221 technical data ? mc68hc908ab32 section 13. programmable interrupt timer (pit) 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 13.4.1 pit counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 13.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 13.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 13.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 13.6 pit during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 224 13.7 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 13.7.1 pit status and control register. . . . . . . . . . . . . . . . . . . . . 225 13.7.2 pit counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 13.7.3 pit counter modulo registers . . . . . . . . . . . . . . . . . . . . . . 228 13.2 introduction this section describes th e programmable interrupt timer (pit), which is a timer whose counter is clocked in ternally via software programmable options. figure 13-1 is a block diagram of the pit.
programmable interrupt timer (pit) technical data mc68hc908ab32 ? rev. 1.1 222 programmable interrupt timer (pit) freescale semiconductor 13.3 features features of the pit include the following: programmable pit clock input free-running or modul o up-count operation pit counter stop and reset bits 13.4 functional description figure 13-1 shows the structure of the pit. the central component of the pit is the 16-bit pit counter that can o perate as a free-running counter or a modulo up-counter. the counter provides the timing reference for the inte rrupt. the pit counter modulo registers, pmodh:pmodl, control th e modulo value of the counter. software can read the counter value at any time without affecting the counting sequence. figure 13-1. pit block diagram prescaler prescaler select 16-bit comparator pps2 pps1 pps0 pof poie pmodh:pmodl prst pstop 16-bit counter internal interrupt logic bus clock
programmable interrupt timer (pit) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor programmable interrupt timer (pit) 223 13.4.1 pit counter prescaler the clock source can be one of t he seven prescaler outputs. the prescaler generates seven clock rate s from the internal bus clock. the prescaler select bits, pps[ 2:0] in the status and control register select the pit clock source. the value in the pit counter modulo registers and the selected prescaler output determines the frequency of the peri odic interrupt. the pit overflow flag (pof) is se t when the pit counter va lue rolls over to $0000 after matching the value in the pi t counter modulo r egisters. the pit interrupt enable bit, poie, enables pit overflow cpu inte rrupt requests. pof and poie are in the pit status and control register. addr.register name bit 7654321bit 0 $004b pit status and control register (psc) read: pof poie pstop 00 pps2 pps1 pps0 write: 0 prst reset:00100000 $004c pit counter register high (pcnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $004d pit counter register low (pcntl) read: bit 7 654321bit 0 write: reset:00000000 $004e pit counter modulo register high (pmodh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 $004f pit counter modulo register low (pmodl) read: bit 7654321bit 0 write: reset:11111111 = unimplemented figure 13-2. pit i /o register summary
programmable interrupt timer (pit) technical data mc68hc908ab32 ? rev. 1.1 224 programmable interrupt timer (pit) freescale semiconductor 13.5 low-power modes the wait and stop in structions put the mcu in low-power- consumption standby modes. 13.5.1 wait mode the pit remains active after the executi on of a wait instruction. in wait mode the pit registers are not accessible by the cpu. any enabled cpu interrupt request from the pit can bring the mcu out of wait mode. if pit functions are not required during wait mode, reduce power consumption by stopping the pit befor e executing the wait instruction. 13.5.2 stop mode the pit is inactive after the executi on of a stop instruction. the stop instruction does no t affect register conditions or the state of the pit counter. pit operation resumes when the mcu exits stop mode after an external interrupt. 13.6 pit during break interrupts a break interrupt st ops the pit counter. the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the sim break flag contro l register (sbfcr) enabl es software to clear status bits during the break state. see 8.8.3 sim break flag control register . to allow software to clear status bi ts during a break interrupt, write a logic one to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits dur ing the break state, writ e a logic zero to the bcfe bit. with bcfe at logic zero (its default state), software can read and write i/o registers during the br eak state without affecting status
programmable interrupt timer (pit) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor programmable interrupt timer (pit) 225 bits. some status bits have a two- step read/write cleari ng procedure. if software does the first step on such a bit before the brea k, the bit cannot change during the break stat e as long as bcfe is at logic zero. after the break, doing the second step clears the status bit. 13.7 i/o registers the following i/o registers control and monitor operation of the pit: pit status and co ntrol register (psc) pit counter registers (pcnth:pcntl) pit counter modulo registers (pmodh:pmodl) 13.7.1 pit status and control register the pit status and control re gister does the following: enables pit interrupt flags pit overflows stops the pit counter resets the pit counter prescales the pit counter clock address: $004b bit 7654321bit 0 read: pof poie pstop 00 pps2 pps1 pps0 write: 0 prst reset: 00100000 = unimplemented figure 13-3. pit status and control register (psc)
programmable interrupt timer (pit) technical data mc68hc908ab32 ? rev. 1.1 226 programmable interrupt timer (pit) freescale semiconductor pof ? pit overflow flag bit this read/write flag is set when the pit counter resets to $0000 after reaching the modul o value programmed in the pit counter modulo registers. clear pof by reading the pit status and control register when pof is set and then writing a lo gic zero to pof. if another pit overflow occurs before the clear ing sequence is complete, then writing logic zero to pof has no effect. therefore, a pof interrupt request cannot be lost du e to inadvertent clea ring of pof. reset clears the pof bit. writing a logic one to pof has no effect. 1 = pit counter has reached modulo value 0 = pit counter has not reached modulo value poie ? pit overflow interrupt enable bit this read/write bit enables pit overflow inte rrupts when the pof bit becomes set. reset clears the poie bit. 1 = pit overflow interrupts enabled 0 = pit overflow interrupts disabled pstop ? pit stop bit this read/write bit stop s the pit counter. counting resumes when pstop is cleared. reset sets the pstop bit, stopping the pit counter until software clears the pstop bit. 1 = pit counter stopped 0 = pit counter active note: do not set the pstop bit before entering wait mode if the pit is required to exit wait mode. prst ? pit reset bit setting this write-only bit resets th e pit counter and t he pit prescaler. setting prst has no effect on any other registers. counting resumes from $0000. prst is cl eared automatically afte r the pit counter is reset and always reads as logic zero. rese t clears the prst bit. 1 = prescaler and pi t counter cleared 0 = no effect note: setting the pstop and prst bits si multaneously stops the pit counter at a value of $0000.
programmable interrupt timer (pit) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor programmable interrupt timer (pit) 227 pps[2:0] ? pit prescaler select bits these read/write bits select one of the seven prescaler outputs as the input to the pit counter as table 13-1 shows. reset clears the pps[2:0] bits. 13.7.2 pit counter registers the two read-only pit counter regist ers contain the high and low bytes of the value in the pit counter. readi ng the high byte (pcnth) latches the contents of the low byte (pcntl) into a buffer. subsequent reads of pcnth do not affect th e latched pcntl value until pcntl is read. reset clears the pit counter register s. setting the pit reset bit (prst) also clears the pi t counter registers. note: if you read pcnth during a break in terrupt, be sure to unlatch pcntl by reading pcntl before exiting the break interrupt. otherwise, pcntl retains the value latc hed during the break. table 13-1. pit prescaler selection pps2 pps1 pps0 pit clock source 0 0 0 internal bus clock 1 0 0 1 internal bus clock 2 0 1 0 internal bus clock 4 0 1 1 internal bus clock 8 1 0 0 internal bus clock 16 1 0 1 internal bus clock 32 1 1 0 internal bus clock 64 1 1 1 internal bus clock 64 address: $004c bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 = unimplemented figure 13-4. pit counte r register high (pcnth)
programmable interrupt timer (pit) technical data mc68hc908ab32 ? rev. 1.1 228 programmable interrupt timer (pit) freescale semiconductor 13.7.3 pit counter modulo registers the read/write pit modulo registers c ontain the modulo value for the pit counter. when the pi t counter reaches the modul o value, the overflow flag (pof) becomes set, and the pi t counter resumes counting from $0000 at the next clock. wr iting to the high byte (pmodh) inhibits the pof bit and overflow inte rrupts until the low byte (pmodl) is written. reset sets the pit counter modulo registers. note: reset the pit counter before writing to the pit counter modulo registers. address: $004d bit 7654321bit 0 read: bit 7 654321bit 0 write: reset:00000000 = unimplemented figure 13-5. pit counter register low (pcntl) address: $004e bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:11111111 figure 13-6. pit counter modulo register high (pmodh) address: $004f bit 7654321bit 0 read: bit 7654321bit 0 write: reset:11111111 figure 13-7. pit counter m odulo register low (pmodl)
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor analog-to-digital converter (adc) 229 technical data ? mc68hc908ab32 section 14. analog-to-digital converter (adc) 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 14.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 14.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 14.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 14.4.4 conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 14.4.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 14.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 14.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 14.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 14.7.1 adc analog power pin (v ddaref ). . . . . . . . . . . . . . . . . . . 234 14.7.2 adc analog ground pin (a vss /v refl ) . . . . . . . . . . . . . . . 234 14.7.3 adc voltage reference high pin (v refh ). . . . . . . . . . . . . 234 14.7.4 adc voltage in (v adin ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 14.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 14.8.1 adc status and control register (adscr). . . . . . . . . . . . 235 14.8.2 adc data register ( adr) . . . . . . . . . . . . . . . . . . . . . . . . . 237 14.8.3 adc clock register (a dclk) . . . . . . . . . . . . . . . . . . . . . . 237
analog-to-digital converter (adc) technical data mc68hc908ab32 ? rev. 1.1 230 analog-to-digital converter (adc) freescale semiconductor 14.2 introduction this section describes the 8-bit analog-to-digital converter (adc). 14.3 features features of the ad c module include: eight channels with multiplexed input linear successive approximation with monotonicity 8-bit resolution single or cont inuous conversion conversion complete flag or conversion complete interrupt selectable adc clock addr.register name bit 7654321bit 0 $0038 adc status and control register (adscr) read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 $0039 adc data register (adr) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset:00000000 $003a adc clock register (adclk) read: adiv2 adiv1 adiv0 adiclk 0000 write: reset:00000000 = unimplemented figure 14-1. adc register summary
analog-to-digital converter (adc) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor analog-to-digital converter (adc) 231 14.4 functional description the adc provides eight pins for sa mpling external sources at pins ptb7/atd7?ptb0/atd0. an analog mult iplexer allows the single adc converter to select one of eigh t adc channels as adc voltage in (v adin ). v adin is converted by the successive approximation register-based analog-to-d igital converter. w hen the conversion is completed, adc places t he result in the adc dat a register and sets a flag or generates an interrupt. (see figure 14-2 .) figure 14-2. adc block diagram internal data bus read ddrbx write ddrbx reset write ptbx read ptbx ptbx ddrbx ptbx interrupt logic channel select adc clock generator conversion complete adc (v adin ) adc clock cgmxclk bus clock adch[4:0] adc data register aien coco disable disable adc channel x adiv[2:0] adiclk voltage in adc i/p channels
analog-to-digital converter (adc) technical data mc68hc908ab32 ? rev. 1.1 232 analog-to-digital converter (adc) freescale semiconductor 14.4.1 adc port i/o pins ptb7/atd7?ptb0/atd0 are general- purpose i/o (input/output) pins that share with the a dc channels. the channel select bits define which adc channel/port pi n will be used as the input signal. the adc overrides the port i /o logic by forcing that pin as input to the adc. the remaining adc channels/po rt pins are controlled by the port i/o logic and can be used as general-p urpose i/o. writes to the port register or ddr will not have any affect on the port pin that is selected by the adc. read of a port pin in use by the adc will return a logic 0. 14.4.2 voltage conversion when the input voltage to the adc equals v refh , the adc converts the signal to $ff (full scale). if the input voltage equals v refl , the adc converts it to $00. i nput voltages between v refh and v refl are a straight-line linear conversion. 14.4.3 conversion time conversion starts after a write to the adscr. one conversion will take between 16 and 17 adc clock cycles . the adivx and adiclk bits should be set to provide a 1-mhz adc clock frequency. 14.4.4 conversion in continuous conversion mode, the adc data regi ster will be filled with new data after each conversion. data from the previ ous conversion will be overwritten whether th at data has been read or not. conversions will continue until the adco bit is cleared. the coco bit is set after the first conversion and will stay se t until the next write of the adc status and control register or the next r ead of the adc da ta register. in single conversion mode, conver sion begins with a write to the adscr. only one conversion occu rs between writes to the adscr. 16 to 17 adc cycles adc frequency conversion time = number of bus cycles = conversion time bus frequency
analog-to-digital converter (adc) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor analog-to-digital converter (adc) 233 14.4.5 accuracy and precision the conversion process is monot onic and has no missing codes. 14.5 interrupts when the aien bit is set, the adc m odule is capable of generating cpu interrupts after each adc conversion. a cpu interrupt is generated if the coco bit is at logic 0. the coco bit is not used as a conversion complete flag when interrupts are enabled. 14.6 low-power modes the wait and stop in struction can put th e mcu in low power- consumption standby modes. 14.6.1 wait mode the adc continues norma l operation during wait mode. any enabled cpu interrupt request fro m the adc can bring t he mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by se tting adch[4:0] bits in the adc status and control register before exec uting the wait instruction. 14.6.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conver sions resume when the mcu exits stop mode afte r an external interrup t. allow one conversion cycle to stabilize th e analog circuitry. 14.7 i/o signals the adc module has eight pi ns shared with port b, ptb7/atd7?ptb0/atd0.
analog-to-digital converter (adc) technical data mc68hc908ab32 ? rev. 1.1 234 analog-to-digital converter (adc) freescale semiconductor 14.7.1 adc analog power pin (v ddaref ) the adc analog portion uses v ddaref as its power pi n. connect the v ddaref pin to the same voltage potential as v dd . external filtering may be necessary to ensure clean v ddaref for good results. note: for maximum noise immunity, route v ddaref carefully and place bypass capacitors as close as possible to the package. 14.7.2 adc analog ground pin (a vss /v refl ) the adc analog port ion uses a vss /v refl as its ground pin. connect the a vss /v refl pin to the same vo ltage potential as v ss . note: route a vss /v refl cleanly to avoid any offset errors. 14.7.3 adc voltage reference high pin (v refh ) v refh is the reference voltage for the adc. 14.7.4 adc voltage in (v adin ) v adin is the input voltage signal from one of the eight adc channels to the adc module. 14.8 i/o registers these i/o registers control and monitor adc operation: adc status and cont rol register (adscr) adc data register (adr) adc clock register (adclk)
analog-to-digital converter (adc) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor analog-to-digital converter (adc) 235 14.8.1 adc status and control register (adscr) function of the adc stat us and control register is described here. coco ? conversions complete when the aien bit is a l ogic 0, the coco is a read-only bit which is set each time a conversion is comp leted except in the continuous conversion mode where it is set after the first c onversion. this bit is cleared whenever the adscr is written or whenever t he adr is read. if the aien bit is a logic 1, the coco becomes a read/write bit, which should be cleared to l ogic 0 for cpu to service the adc interrupt request. reset clears the coco bit. 1 = conversion completed (aien=0) 0 = conversion not completed (a ien=0)/cpu interrupt (aien=1) aien ? adc interrupt enable bit when this bit is set, an interrupt is generated at the end of an adc conversion. the interrupt signal is cl eared when the dat a register is read or the status/control register is written.re set clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled adco ? adc continuous conversion bit when set, the adc will convert sa mples continuously and update the adr register at the end of each conversion. only one conversion is completed between writes to the adscr when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion address: $0038 bit 7654321bit 0 read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 figure 14-3. adc status and contro l register (adscr)
analog-to-digital converter (adc) technical data mc68hc908ab32 ? rev. 1.1 236 analog-to-digital converter (adc) freescale semiconductor adch[4:0] ? adc channel select bits adch[4:0] form a 5-bit field which is used to select one of the eight adc channels, atd7?atd0. the channels are detailed in table 14-1 . care should be ta ken when using a port pin as both an analog and digital input si multaneously to prev ent switching noise from corrupting the analog signal. the adc subsystem is turned off w hen the channel select bits are all set to 1. this feature allows for reduced power cons umption for the mcu when the adc is not being used. note: recovery from the disabled stat e requires one conversion cycle to stabilize. the voltage levels suppli ed from internal refer ence nodes, as specified in table 14-1 , are used to verify the operati on of the adc converter both in production test and for user applications. table 14-1. mux channel select adch4 adch3 adch2 adch1 adch0 input select 00000 ptb0/atd0 00001 ptb1/atd1 00010 ptb2/atd2 00011 ptb3/atd3 00100 ptb4/atd4 00101 ptb5/atd5 00110 ptb6/atd6 00111 ptb7/atd7 01000 reserved 11100 11101 v refh 11110 v refl 11111adc power off note: if any unused channels are selected, th e resulting adc conversion will be unknown or reserved.
analog-to-digital converter (adc) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor analog-to-digital converter (adc) 237 14.8.2 adc data register (adr) one 8-bit result regist er, adc data register (a dr), is provided. this register is updated each time an adc conversion completes. 14.8.3 adc clock register (adclk) the adc clock register (adclk) se lects the clock frequency for the adc. adiv[2:0] ? adc clock prescaler bits adiv[2:0] form a 3-bit field which selects the divide ratio used by the adc to generate the in ternal adc clock. table 14-2 shows the available clock configurations. the adc clock shou ld be set to approximately 1 mhz. address: $0039 bit 7654321bit 0 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset:00000000 = unimplemented figure 14-4. adc data register (adr) address: $003a bit 7654321bit 0 read: adiv2 adiv1 adiv0 adiclk 0000 write: reset:00000000 = unimplemented figure 14-5. adc clock register (adclk)
analog-to-digital converter (adc) technical data mc68hc908ab32 ? rev. 1.1 238 analog-to-digital converter (adc) freescale semiconductor adiclk ? adc input clock select bit adiclk selects either the bus cloc k or cgmxclk as the input clock source to generate the internal adc clock. reset selects cgmxclk as the adc clock source. if the external clock (cgmxclk) is equal to or grea ter than 1 mhz, cgmxclk can be used as the cl ock source for the adc. if cgmxclk is less than 1 mhz, use the pll-generated bus clock as the clock source. as long as t he internal adc clock is at approximately 1 mhz, correct operation can be guaranteed. 1 = internal bus clock 0 = external clock (cgmxclk) table 14-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 adc input clock 1 0 0 1 adc input clock 2 0 1 0 adc input clock 4 0 1 1 adc input clock 8 1 x x adc input clock 16 x = don?t care adc input clock frequency adiv[2:0] ------------------ ---------------------- --------------------- ---------- 1 m h z =
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 239 technical data ? mc68hc908ab32 section 15. serial communications interface module (sci) 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 15.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 15.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 15.5.1 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 15.5.2 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 15.5.2.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 15.5.2.2 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . 247 15.5.2.3 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 15.5.2.4 idle characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 15.5.2.5 inversion of transm itted output. . . . . . . . . . . . . . . . . . . 249 15.5.2.6 transmitter in terrupts. . . . . . . . . . . . . . . . . . . . . . . . . . .249 15.5.3 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 15.5.3.1 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 15.5.3.2 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 15.5.3.3 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 15.5.3.4 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 15.5.3.5 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . .254 15.5.3.6 receiver wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 15.5.3.7 receiver interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 15.5.3.8 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 15.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 15.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 15.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 15.7 sci during break module interrupts. . . . . . . . . . . . . . . . . . . .260 15.8 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 15.8.1 pte0/txd (transmit data). . . . . . . . . . . . . . . . . . . . . . . . . 260
serial communications interface technical data mc68hc908ab32 ? rev. 1.1 240 serial communications interface module (sci) freescale semiconductor 15.8.2 pte1/rxd (receive data ) . . . . . . . . . . . . . . . . . . . . . . . . . 260 15.9 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 15.9.1 sci control regi ster 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 15.9.2 sci control regi ster 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 15.9.3 sci control regi ster 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 15.9.4 sci status register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 15.9.5 sci status register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 15.9.6 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 15.9.7 sci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . .275 15.2 introduction this section describes the serial communications interface (sci) module, which allows hi gh-speed asynchronous communications with peripheral devices and other mcus. note: references to dma (direct-memory access) and associated functions are only valid if t he mcu has a dma module. this mcu does not have the dma function. any dma -related register bits sh ould be left in their reset state for normal mcu operation. 15.3 features features of the sci modu le include the following: full-duplex operation standard mark/space non-re turn-to-zero (nrz) format 32 programmable baud rates programmable 8-bit or 9-bit character length separately enabled trans mitter and receiver separate receiver and transmi tter cpu interrupt requests programmable transm itter output polarity
serial communications interface module (sci) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 241 two receiver wakeup methods: ? idle line wakeup ? address mark wakeup interrupt-driven operation with eight interrupt flags: ? transmitter empty ? transmission complete ? receiver full ? idle receiver input ? receiver overrun ? noise error ? framing error ? parity error receiver framin g error detection hardware parity checking 1/16 bit-time noise detection
serial communications interface technical data mc68hc908ab32 ? rev. 1.1 242 serial communications interface module (sci) freescale semiconductor 15.4 pin name conventions the generic names of th e sci i/o pins are: rxd (receive data) txd (transmit data) sci i/o (input/outpu t) lines are implemented by sharing parallel i/o port pins. the full name of an sci input or output re flects the name of the shared port pin. table 15-1 shows the full names and the generic names of the sci i/o pins. the generic pin names appear in t he text of this section. 15.5 functional description figure 15-1 shows the structure of the sc i module. the sci allows full- duplex, asynchronous, nrz serial communication among the mcu and remote devices, including other mcus . the transmitter and receiver of the sci operate independent ly, although they us e the same baud rate generator. during normal oper ation, the cpu monitors the status of the sci, writes the data to be transmi tted, and processes received data. table 15-1. pin name conventions generic pin names: rxd txd full pin names: pte1/rxd pte0/txd
serial communications interface module (sci) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 243 figure 15-1. sci m odule block diagram scte tc scrf idle or nf fe pe sctie tcie scrie ilie te re rwu sbk r8 t8 r orie feie peie bkf rpf sci data receive shift register sci data register transmit shift register neie m wake ilty flag control transmit control receive control data selection control wakeup pty pen register dma interrupt control transmitter interrupt control receiver interrupt control error interrupt control control r ensci loops ensci pte1/rxd pte0/txd internal bus txinv loops 4 16 pre- scaler baud divider cgmxclk
serial communications interface technical data mc68hc908ab32 ? rev. 1.1 244 serial communications interface module (sci) freescale semiconductor addr.register name bit 7654321bit 0 $0013 sci control register 1 (scc1) read: loops ensci txinv m wake ilty pen pty write: reset:00000000 $0014 sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 $0015 sci control register 3 (scc3) read: r8 t8 r r orie neie feie peie write: reset:uu000000 $0016 sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: reset:11000000 $0017 sci status register 2 (scs2) read: bkf rpf write: reset:00000000 $0018 sci data register (scdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset $0019 sci baud rate register (scbr) read: scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 = unimplemented r = reserved u = unaffected figure 15-2. sci i/ o register summary
serial communications interface module (sci) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 245 15.5.1 data format the sci uses the standard non-return-to-zero mark /space data format illustrated in figure 15-3 . figure 15-3. sci data formats 15.5.2 transmitter figure 15-4 shows the structure of the sci transmitter. bit 5 start bit bit 0 bit 1 next stop bit start bit 8-bit data format bit m in scc1 clear start bit bit 0 next stop bit start bit 9-bit data format bit m in scc1 set bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 parity bit parity bit
serial communications interface technical data mc68hc908ab32 ? rev. 1.1 246 serial communications interface module (sci) freescale semiconductor figure 15-4. sci transmitter r scte pen pty h876543210l 11-bit transmit stop start t8 r scte sctie tcie sbk tc parity generation msb sci data register load from scdr shift enable preamble all 1s break all 0s transmitter control logic shift register r tc sctie tcie scte transmitter cpu interrupt request transmitter dma service request m ensci loops te pte0/txd txinv internal bus 4 pre- scaler scp1 scp0 scr2 scr1 scr0 baud divider 16 sctie cgmxclk
serial communications interface module (sci) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 247 15.5.2.1 character length the transmitter can accommod ate either 8-bit or 9- bit data. the state of the m bit in sci control register 1 (scc1) deter mines character length. when transmitting 9-bit data, bit t8 in sci control register 3 (scc3) is the ninth bi t (bit 8). 15.5.2.2 character transmission during an sci transmission, the transmit shift regist er shifts a character out to the pte0/txd pin. the sci dat a register (scdr) is the write-only buffer between the internal data bus and the transmi t shift register. to initiate an sci transmission: 1. enable the sci by writing a logi c 1 to the enable sci bit (ensci) in sci control r egister 1 (scc1). 2. enable the transmitter by writi ng a logic 1 to the transmitter enable bit (te) in sci cont rol register 2 (scc2). 3. clear the sci transmit ter empty bit by first reading sci status register 1 (scs1) and t hen writing to the scdr. 4. repeat step 3 for each subsequent transmission. at the start of a transmission, tran smitter control logic automatically loads the transmit shift register with a preamble of logic 1s. after the preamble shifts out, control logic tr ansfers the scdr data into the transmit shift register. a logic 0 start bit automati cally goes into the least significant bit position of the transmit shift register. a lo gic 1 stop bit goes into the most signi ficant bit position. the sci transmitter empt y bit, scte, in scs1 becomes set when the scdr transfers a byte to the trans mit shift register. the scte bit indicates that the scdr c an accept new data from the internal data bus. if the sci transmit interrupt enable bit, sctie, in scc2 is also set, the scte bit generates a transmi tter cpu interrupt request. when the transmit shift register is not transmitting a character, the pte0/txd pin goes to the idle condition, logic 1. if at any time software clears the ensci bit in sci control register 1 (s cc1), the transmitter and receiver relinquish contro l of the port e pins.
serial communications interface technical data mc68hc908ab32 ? rev. 1.1 248 serial communications interface module (sci) freescale semiconductor 15.5.2.3 break characters writing a logic 1 to the send break bit, sbk, in scc2 loads the transmit shift register with a break character. a break character contains all logic 0s and has no start, stop, or parity bit. break character length depends on the m bit in scc1. as long as sbk is at logi c 1, transmitter logic continuously loads break characters in to the transmit shif t register. after software clears the sbk bit, the shif t register finishes transmitting the last break character and then tr ansmits at least one logic 1. the automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the nex t character. the sci recognizes a break characte r when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. receiving a break character has these effects on sci registers: sets the framing erro r bit (fe) in scs1 sets the sci receiver full bit (scrf) in scs1 clears the sci dat a register (scdr) clears the r8 bit in scc3 sets the break flag bit (bkf) in scs2 may set the overrun (or), noise flag (nf), parity error (pe), or reception in prog ress flag (rpf) bits 15.5.2.4 idle characters an idle character contains all logic 1s and has no st art, stop, or parity bit. idle character length depends on the m bit in scc1. th e preamble is a synchronizing idle character that begins every transmission. if the te bit is cleared during a tr ansmission, the pte0/txd pin becomes idle after completion of the transmission in pr ogress. clearing and then setting the te bit duri ng a transmission queues an id le character to be sent after the character currently being transmitted.
serial communications interface module (sci) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 249 note: when queueing an idle character, return the te bit to logic 1 before the stop bit of the current c haracter shifts out to the txd pin. setting te after the stop bit appears on txd causes da ta previously wr itten to the scdr to be lost. toggle the te bit for a queued idle character when the scte bit becomes set and just be fore writing the nex t byte to the scdr. 15.5.2.5 inversion of transmitted output the transmit inversion bit (txinv) in sci control r egister 1 (scc1) reverses the polarity of transmitted da ta. all transmitted values, including idle, break, start, and stop bits, are inverted when txinv is at logic 1. (see 15.9.1 sci control register 1 .) 15.5.2.6 transmitter interrupts these conditions can ge nerate cpu interrupt requests from the sci transmitter: sci transmitter empty (scte) ? the scte bit in scs1 indicates that the scdr has transferred a character to the transmit shift register. scte can gene rate a transmitter cp u interrupt request. setting the sci transmit interrupt enable bit, sctie, in scc2 enables the scte bit to generat e transmitter cpu interrupt requests. transmission complete (tc) ? the tc bit in scs1 indicates that the transmit shift register and the scdr are em pty and that no break or idle character has been generated. th e transmission complete interrupt enable bit, tcie , in scc2 enables the tc bit to generate transmitter cpu interrupt requests.
serial communications interface technical data mc68hc908ab32 ? rev. 1.1 250 serial communications interface module (sci) freescale semiconductor 15.5.3 receiver figure 15-5 shows the structure of the sci receiver. 15.5.3.1 character length the receiver can accommodat e either 8-bit or 9-bi t data. the state of the m bit in sci control register 1 (scc1) determines character length. when receiving 9-bit data, bit r8 in sci control register 2 (scc2) is the ninth bit (bit 8). when rece iving 8-bit data, bit r8 is a copy of the eighth bit (bit 7). 15.5.3.2 character reception during an sci re ception, the receive shift regi ster shifts characters in from the pte1/rxd pin. the sci data register (scdr) is the read-only buffer between the inter nal data bus and the re ceive shift register. after a complete character shifts into the receive shift register, the data portion of the character transfers to the scdr. the sci receiver full bit, scrf, in sci status regi ster 1 (scs1) becomes se t, indicating that the received byte can be read. if the sci receive interrupt enable bit, scrie, in scc2 is also set, the scrf bi t generates a receiver cpu interrupt request.
serial communications interface module (sci) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 251 figure 15-5. sci receiver block diagram all 1s all 0s m wake ilty pen pty bkf rpf h876543210l 11-bit receive shift register stop start data recovery r scrf or orie nf neie fe feie pe peie r scrie scrf ilie idle wakeup logic parity checking msb error cpu interrupt request dma service request cpu interrupt request sci data register r8 r orie neie feie peie scrie ilie rwu scrf idle or nf fe pe pte1/rxd internal bus pre- scaler baud divider 4 16 scp1 scp0 scr2 scr1 scr0 scrie r cgmxclk
serial communications interface technical data mc68hc908ab32 ? rev. 1.1 252 serial communications interface module (sci) freescale semiconductor 15.5.3.3 data sampling the receiver samples the pte1/rxd pin at the rt clock rate. the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock is resynchronized at the following times (see figure 15-6 ): after every start bit after the receiver detects a data bit change from l ogic 1 to logic 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid logic 1 and the majority of t he next rt8, rt9, and rt10 samples returns a valid logic 0) to locate the start bit, data recovery logic does an asyn chronous search for a logic 0 preceded by three logic 1s. when the falling edge of a possible start bit occurs, the rt clock begins to count to 16. figure 15-6. receiver data sampling rt clock reset rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 start bit qualification start bit verification data sampling samples rt clock rt clock state start bit lsb pte1/rxd
serial communications interface module (sci) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 253 to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 15-2 summarizes t he results of the start bit verification samples. start bit verification is not successful if any two of the three verification samples are logic 1s. if start bit ve rification is not successful, the rt clock is reset and a new search for a start bit begins. to determine the value of a data bit and to detect noise, recovery logic takes samples at r t8, rt9, and rt10. table 15-3 summarizes the results of the data bit samples. table 15-2. start bit verification rt3, rt5, and rt7 samples start bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 table 15-3. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0
serial communications interface technical data mc68hc908ab32 ? rev. 1.1 254 serial communications interface module (sci) freescale semiconductor note: the rt8, rt9, and rt10 samp les do not affect star t bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are logic 1s following a successful start bit verifica tion, the noise flag (nf) is set and the receiver assumes that the bit is a start bit. to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 15-4 summarizes the resu lts of the stop bit samples. 15.5.3.4 framing errors if the data recovery l ogic does not detect a logi c 1 where the stop bit should be in an in coming character, it sets t he framing error bit, fe, in scs1. a break character also sets t he fe bit because a break character has no stop bit. the fe bit is set at the same time that t he scrf bit is set. 15.5.3.5 baud rate tolerance a transmitting device may be operat ing at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit. then a noise error occurs. if more t han one of the samples is outside the stop bit, a framing error occurs. in most applications, the baud rate table 15-4. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0
serial communications interface module (sci) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 255 tolerance is much more than the degree of misalignm ent that is likely to occur. as the receiver samples an incoming character, it resynchronizes the rt clock on any valid falling edge within the character. resynchronization within characters corrects misali gnments between trans mitter bit times and receiver bit times. slow data tolerance figure 15-7 shows how much a slow received character can be misaligned without causing a noise error or a fr aming error. the slow stop bit begins at rt8 instead of rt1 but arrives in time for the stop bit data samples at r t8, rt9, and rt10. figure 15-7. slow data for an 8-bit character, data sampling of the st op bit takes the receiver 9 bit times 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 15-7 , the receiver counts 154 rt cycles at the point when the count of t he transmitting device is 9 bit times 16 rt cycles + 3 rt cycles = 147 rt cycles. the maximum percent diff erence between the re ceiver count and the transmitter count of a slow 8- bit character with no errors is for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. msb stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 147 ? 154 ------------- ------------ - 100 4.54% =
serial communications interface technical data mc68hc908ab32 ? rev. 1.1 256 serial communications interface module (sci) freescale semiconductor with the misaligned character shown in figure 15-7 , the receiver counts 170 rt cycles at the point when the count of t he transmitting device is 10 bit times 16 rt cycles + 3 rt cycles = 163 rt cycles. the maximum percent diff erence between the re ceiver count and the transmitter count of a slow 9- bit character with no errors is fast data tolerance figure 15-8 shows how much a fast received character can be misaligned without causing a noise error or a framing erro r. the fast stop bit ends at rt10 instead of rt16 but is st ill there for t he stop bit data samples at rt8, rt9, and rt10. figure 15-8. fast data for an 8-bit character, data sampling of the st op bit takes the receiver 9 bit times 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 15-8 , the receiver counts 154 rt cycles at the point when the count of t he transmitting device is 10 bit times 16 rt cycles = 160 rt cycles. the maximum percent diff erence between the re ceiver count and the transmitter count of a fast 8-bi t character with no errors is 170 163 ? 170 ------------- ------------ - 100 4.12% = idle or next character stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 160 ? 154 ------------- ------------ - 100 3.90% =
serial communications interface module (sci) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 257 for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 15-8 , the receiver counts 170 rt cycles at the point when the count of t he transmitting device is 11 bit times 16 rt cycles = 176 rt cycles. the maximum percent diff erence between the re ceiver count and the transmitter count of a fast 9- bit character with no errors is 15.5.3.6 receiver wakeup so that the mcu can ignore tr ansmissions intended only for other receivers in multiple-receiver system s, the receiver can be put into a standby state. setting the receiver wa keup bit, rwu, in scc2 puts the receiver into a standby state during which re ceiver interrupts are disabled. depending on the state of the wake bit in scc1, either of two conditions on the pte1/rxd pin can bring the receiv er out of the standby state: address mark ? an address mark is a logic 1 in the most significant bit position of a rece ived character. when the wake bit is set, an address mark wakes t he receiver from the standby state by clearing the rwu bit. the addr ess mark also sets the sci receiver full bit, scrf. software can then compare the character containing the address mark to the user-defined address of the receiver. if they ar e the same, the receiv er remains awake and processes the characters that fo llow. if they are not the same, software can set the rwu bit and put the rece iver back into the standby state. idle input line condition ? when the wake bit is clear, an idle character on the pte1/rxd pin wakes the receiver from the standby state by clearing the rw u bit. the idle character that wakes the receiver does not set the receiver idle bit, idle, or the 170 176 ? 170 ------------ ------------- - 100 3.53% =
serial communications interface technical data mc68hc908ab32 ? rev. 1.1 258 serial communications interface module (sci) freescale semiconductor sci receiver full bit, scrf. the id le line type bit, ilty, determines whether the receiver begins counting logic 1s as idle character bits after the start bit or after the stop bit. note: with the wake bit clear , setting the rwu bit afte r the rxd pin has been idle may cause the receiver to wake up immediately. 15.5.3.7 receiver interrupts the following sources can gene rate cpu interrupt re quests from the sci receiver: sci receiver full ( scrf) ? the scrf bit in scs1 indicates that the receive shift register has tran sferred a characte r to the scdr. scrf can generate a receiver cp u interrupt request. setting the sci receive interrupt enable bit, s crie, in scc2 enables the scrf bit to generate rece iver cpu interrupts. idle input (idle) ? the idle bit in scs1 i ndicates that 10 or 11 consecutive logic 1s shifted in from the pte1/rxd pin. the idle line interrupt enable bi t, ilie, in scc2 enables the idle bit to generate cpu inte rrupt requests. 15.5.3.8 error interrupts the following receiver error flags in scs1 can generat e cpu interrupt requests: receiver overrun (or) ? the or bit indicates that the receive shift register shifted in a new character before the previous character was read from the scdr. the previous character remains in the scdr, and the new character is lost. the overrun interrupt enable bit, orie, in scc3 enables or to generate sci error cpu interrupt requests. noise flag (nf) ? the nf bit is set when the sci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enabl e bit, neie, in scc3 enables nf to generate sci erro r cpu interrupt requests.
serial communications interface module (sci) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 259 framing error (fe) ? the fe bit in scs1 is se t when a logic 0 occurs where the receiver expec ts a stop bit. the framing error interrupt enable bit, feie, in scc3 enables fe to generate sci error cpu interrupt requests. parity error (pe) ? the pe bit in scs1 is set when the sci detects a parity error in incoming data. the parity error interrupt enable bit, peie, in scc3 enables pe to gener ate sci error cpu interrupt requests. 15.6 low-power modes the wait and stop in structions put the mcu in low power- consumption standby modes. 15.6.1 wait mode the sci module remains active af ter the execution of a wait instruction. in wait m ode, the sci module register s are not accessible by the cpu. any enabled c pu interrupt request fr om the sci module can bring the mcu out of wait mode. if sci module functions are not requ ired during wait mode, reduce power consumption by disabling the m odule before executing the wait instruction. refer to 8.7 low-power modes for information on ex iting wait mode. 15.6.2 stop mode the sci module is inactive after the execution of a st op instruction, and thus the sci cannot cause an interr upt to exit stop mode. the stop instruction does not affect sci register st ates. sci module operation resumes after an external interrupt. because the internal clock is inacti ve during stop m ode, entering stop mode during an sci transmission or reception results in invalid data. refer to 8.7 low-power modes for information on exiting stop mode.
serial communications interface technical data mc68hc908ab32 ? rev. 1.1 260 serial communications interface module (sci) freescale semiconductor 15.7 sci during break module interrupts the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the sim break flag contro l register (sbfcr) enabl es software to clear status bits during the break state. to allow software to clear status bi ts during a break interrupt, write a logic 1 to the bcfe bit. if a status bi t is cleared during t he break state, it remains cleared when the m cu exits the break state. to protect status bits du ring the break state, writ e a logic 0 to the bcfe bit. with bcfe at logic 0 (its defaul t state), software can read and write i/o registers during the break state wi thout affecting status bits. some status bits have a 2-st ep read/write clearing proced ure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. 15.8 i/o signals port e shares two of its pins with the sci module. the two sci i/o pins are: pte0/txd ? transmit data pte1/rxd ? receive data 15.8.1 pte0/txd (transmit data) the pte0/txd pin is the serial data output from the sci transmitter. the sci shares the pte0/txd pin with po rt e. when the sci is enabled, the pte0/txd pin is an output regardless of the state of the ddre2 bit in data direction register e (ddre). 15.8.2 pte1/rxd (receive data) the pte1/rxd pin is the serial data input to the sci receiver. the sci shares the pte1/rxd pin with port e. when th e sci is enabled, the pte1/rxd pin is an input regardless of the state of the ddre1 bit in data direction register e (ddre).
serial communications interface module (sci) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 261 15.9 i/o registers these i/o registers control and monitor sci operation: sci control register 1 (scc1) sci control register 2 (scc2) sci control register 3 (scc3) sci status register 1 (scs1) sci status register 2 (scs2) sci data register (scdr) sci baud rate register (scbr) 15.9.1 sci control register 1 sci control register 1: enables loop mode operation enables the sci controls output polarity controls character length controls sci wakeup method controls idle character detection enables parity function controls parity type
serial communications interface technical data mc68hc908ab32 ? rev. 1.1 262 serial communications interface module (sci) freescale semiconductor loops ? loop mode select bit this read/write bit enabl es loop mode operatio n. in loop mode the pte1/rxd pin is disconnected from the sci, and the transmitter output goes into the rece iver input. both t he transmitter and the receiver must be enabled to use loop mode. reset clears the loops bit. 1 = loop mode enabled 0 = normal operation enabled ensci ? enable sci bit this read/write bit enabl es the sci and the sc i baud rate generator. clearing ensci sets the scte and tc bits in sc i status register 1 and disables transmitter interrupt s. reset clears the ensci bit. 1 = sci enabled 0 = sci disabled txinv ? transmit inversion bit this read/write bit reverses the polarity of transmitted data. reset clears the txinv bit. 1 = transmitter output inverted 0 = transmitter out put not inverted note: setting the txinv bit inve rts all transmitted values , including idle, break, start, and stop bits. address: $0013 bit 7654321bit 0 read: loops ensci txinv m wake ilty pen pty write: reset:00000000 figure 15-9. sci cont rol register 1 (scc1)
serial communications interface module (sci) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 263 m ? mode (character length) bit this read/write bit deter mines whether sci characters are eight or nine bits long. (see table 15-5 .) the ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. reset clears the m bit. 1 = 9-bit sci characters 0 = 8-bit sci characters wake ? wakeup condition bit this read/write bit deter mines which condition wakes up the sci: a logic 1 (address mark) in the most si gnificant bit posi tion of a received character or an idle condition on t he pte1/rxd pin. reset clears the wake bit. 1 = address mark wakeup 0 = idle line wakeup ilty ? idle line type bit this read/write bit deter mines when the sci star ts counting logic 1s as idle character bits. the counting begins either after the start bit or after the stop bit. if the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. beginning the count after the stop bit avoids false idle character recognition, but re quires properly synchronized transmissions. reset clears the ilty bit. 1 = idle character bit c ount begins afte r stop bit 0 = idle character bit c ount begins after start bit pen ? parity enable bit this read/write bit ena bles the sci pari ty function. (see table 15-5 .) when enabled, the parity function in serts a parity bit in the most significant bit position. (see figure 15-3 .) reset clears the pen bit. 1 = parity function enabled 0 = parity function disabled
serial communications interface technical data mc68hc908ab32 ? rev. 1.1 264 serial communications interface module (sci) freescale semiconductor pty ? parity bit this read/write bit determines w hether the sci generates and checks for odd parity or even parity. (see table 15-5 .) reset clears the pty bit. 1 = odd parity 0 = even parity note: changing the pty bit in the middle of a transmission or reception can generate a parity error. 15.9.2 sci control register 2 sci control register 2: enables the following cpu interrupt requests: ? enables the scte bit to gener ate transmitter cpu interrupt requests ? enables the tc bi t to generate transmi tter cpu interrupt requests ? enables the scrf bit to gener ate receiver cpu interrupt requests ? enables the idle bit to gene rate receiver cpu interrupt requests table 15-5. character format selection control bits character format m pen and pty start bits data bits parity stop bits character length 0 0x 1 8 none 1 10 bits 1 0x 1 9 none 1 11 bits 0 10 1 7 even 1 10 bits 0 11 1 7 odd 1 10 bits 1 10 1 8 even 1 11 bits 1 11 1 8 odd 1 11 bits
serial communications interface module (sci) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 265 enables the transmitter enables the receiver enables sci wakeup transmits sci break characters sctie ? sci transmit interrupt enable bit this read/write bi t enables the scte bit to generate sci transmitter cpu interrupt requests. re set clears t he sctie bit. 1 = scte enabled to generate cpu interrupt 0 = scte not enabled to generate cpu interrupt tcie ? transmission comple te interrupt enable bit this read/write bit enable s the tc bit to generat e sci transmitter cpu interrupt requests. reset clears the tcie bit. 1 = tc enabled to generate cpu interrupt requests 0 = tc not enabled to generate cpu interrupt requests scrie ? sci receive interrupt enable bit this read/write bi t enables the scrf bit to generate sci receiver cpu interrupt requests. re set clears t he scrie bit. 1 = scrf enabled to generate cpu interrupt 0 = scrf not enabled to generate cpu interrupt ilie ? idle line interrupt enable bit this read/write bit enables the idle bit to gener ate sci receiver cpu interrupt requests. rese t clears the ilie bit. 1 = idle enabled to generate cpu interrupt requests 0 = idle not enabl ed to generate cp u interrupt requests address: $0014 bit 7654321bit 0 read: sctie tcie scrie ilie te re rwu sbk write: reset:00000000 figure 15-10. sci cont rol register 2 (scc2)
serial communications interface technical data mc68hc908ab32 ? rev. 1.1 266 serial communications interface module (sci) freescale semiconductor te ? transmitt er enable bit setting this read/write bit begin s the transmission by sending a preamble of 10 or 11 logi c 1s from the transmit shift register to the pte0/txd pin. if software clears t he te bit, the transmitter completes any transmission in progress before th e pte0/txd returns to the idle condition (logic 1). clearing and then setting te during a transmission queues an idle character to be sent after the character currently being transmitted. reset clears the te bit. 1 = transmitt er enabled 0 = transmitt er disabled note: writing to the te bit is not allowed when the enab le sci bit (ensci) is clear. ensci is in sci control register 1. re ? receiver enable bit setting this read/write bit enables the receiver. clearing the re bit disables the receiver but does not a ffect receiver interrupt flag bits. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled note: writing to the re bit is not allowed w hen the enable sci bit (ensci) is clear. ensci is in sci control register 1. rwu ? receiver wakeup bit this read/write bit puts the receiver in a st andby state during which receiver interrupt s are disabled. the wake bit in scc1 determines whether an idle input or an address mark brings the receiver out of the standby state and clear s the rwu bit. rese t clears the rwu bit. 1 = standby state 0 = normal operation
serial communications interface module (sci) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 267 sbk ? send break bit setting and then clearing this r ead/write bit transmits a break character followed by a logic 1. the logic 1 after the break character guarantees recognition of a valid start bit. if sbk remains set, the transmitter continuously transmits break characters with no logic 1s between them. reset clears the sbk bit. 1 = transmit break characters 0 = no break charac ters being transmitted note: do not toggle the sbk bi t immediately after se tting the scte bit. toggling sbk before the preamble begins causes the sci to send a break character instead of a preamble. 15.9.3 sci control register 3 sci control register 3: stores the ninth sci data bit rece ived and the ninth sci data bit to be transmitted enables these interrupts: ? receiver overrun interrupts ? noise error interrupts ? framing error interrupts parity error interrupts address: $0015 bit 7654321bit 0 read: r8 t8 r r orie neie feie peie write: reset:uu000000 = unimplemented r = reserved u = unaffected figure 15-11. sci cont rol register 3 (scc3)
serial communications interface technical data mc68hc908ab32 ? rev. 1.1 268 serial communications interface module (sci) freescale semiconductor r8 ? received bit 8 when the sci is receiving 9-bit char acters, r8 is the read-only ninth bit (bit 8) of the received characte r. r8 is received at the same time that the scdr receiv es the other 8 bits. when the sci is receiving 8-bit charac ters, r8 is a copy of the eighth bit (bit 7). reset has no effect on the r8 bit. t8 ? transmitted bit 8 when the sci is transmi tting 9-bit characters , t8 is the read/write ninth bit (bit 8) of the transmitted character. t8 is loaded into the transmit shift register at the same time that the scdr is loaded into the transmit shift register. re set has no effect on the t8 bit. orie ? receiver overr un interrupt enable bit this read/write bit enabl es sci error cpu interrupt requests generated by the receiver overrun bit, or. 1 = sci error cpu interrupt r equests from or bit enabled 0 = sci error cpu interrupt r equests from or bit disabled neie ? receiver noise error interrupt enable bit this read/write bit enabl es sci error cpu interrupt requests generated by the noise error bi t, ne. reset clears neie. 1 = sci error cpu interrupt r equests from ne bit enabled 0 = sci error cpu interrupt r equests from ne bit disabled feie ? receiver framing error interrupt enable bit this read/write bit enabl es sci error cpu interrupt requests generated by the framing error bit, fe. reset clears feie. 1 = sci error cpu interrupt requests from fe bit enabled 0 = sci error cpu interrupt r equests from fe bit disabled peie ? receiver parity error interrupt enable bit this read/write bit enables sci receiver cpu interrupt requests generated by the par ity error bit, pe. (see 15.9.4 sci status register 1 .) reset clears peie. 1 = sci error cpu interrupt r equests from pe bit enabled 0 = sci error cpu interrupt r equests from pe bit disabled
serial communications interface module (sci) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 269 15.9.4 sci status register 1 sci status register 1 (s cs1) contains flags to signal these conditions: transfer of scdr data to trans mit shift register complete transmission complete transfer of receive shift r egister data to scdr complete receiver input idle receiver overrun noisy data framing error parity error scte ? sci transmi tter empty bit this clearable, read-only bit is set when the scdr transfers a character to the transmit shift register. scte can generate an sci transmitter cpu interrupt request. when the sctie bit in scc2 is set, scte generates an sci transmitter cpu interrupt request. in normal operation, clear the sct e bit by reading sc s1 with scte set and then writing to scdr. re set sets the scte bit. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register address: $0016 bit 7654321bit 0 read: scte tc scrf idle or nf fe pe write: reset:11000000 = unimplemented figure 15-12. sci status register 1 (scs1)
serial communications interface technical data mc68hc908ab32 ? rev. 1.1 270 serial communications interface module (sci) freescale semiconductor tc ? transmission complete bit this read-only bit is set when the sc te bit is set, and no data, preamble, or break character is being transmitted. tc generates an sci transmitter cpu interrupt request if the tcie bit in scc2 is also set. tc is automatically cleared when data, preambl e or break is queued and ready to be sent. there may be up to 1.5 transmitter clocks of latency between queuei ng data, preambl e, and break and the transmission actually star ting. reset sets the tc bit. 1 = no transmission in progress 0 = transmission in progress scrf ? sci receiver full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the sci data register. scrf c an generate an sci receiver cpu interrupt request. w hen the scrie bit in scc2 is set, scrf generates a cpu inte rrupt request. in norm al operation, clear the scrf bit by readi ng scs1 with scrf set and then reading the scdr. reset clears scrf. 1 = received data available in scdr 0 = data not available in scdr idle ? receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. idle generates an sci error cpu interrupt request if the ilie bit in s cc2 is also set. clear the idle bit by reading scs1 with idle set a nd then reading the scdr. after the receiver is enabled, it must receive a valid c haracter that sets the scrf bit before an idle condition can set the idle bit. also, after the idle bit has been cleared, a valid character must again set the scrf bit before an idle condition can set the idle bit. rese t clears the idle bit. 1 = receiver input idle 0 = receiver input active (or id le since the idle bit was cleared) or ? receiver overrun bit this clearable, read-only bit is se t when software fails to read the scdr before the receive shift regist er receives the next character. the or bit generates an sci error cpu interrupt request if the orie
serial communications interface module (sci) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 271 bit in scc3 is also set. the data in the shift regist er is lost, but the data already in the scdr is not affected. clear the or bit by reading scs1 with or set and then reading the scdr. rese t clears the or bit. 1 = receive shift register full and scrf = 1 0 = no receiver overrun software latency may allow an over run to occur between reads of scs1 and scdr in the fl ag-clearing sequence. figure 15-13 shows the normal flag- clearing sequence and an example of an overrun caused by a delayed flag-clearin g sequence. the delayed read of scdr does not clear t he or bit because or was not set when scs1 was read. byte 2 caused the ov errun and is lost. the next flag- clearing sequence read s byte 3 in the scd r instead of byte 2. in applications that are subject to software la tency or in which it is important to know which byte is lost due to an ov errun, the flag- clearing routine c an check the or bit in a se cond read of scs1 after reading the data register. nf ? receiver noise flag bit this clearable, read-only bit is set when the sci detects noise on the pte1/rxd pin. nf generates an nf cpu interrupt request if the neie bit in scc3 is also se t. clear the nf bit by reading scs1 and then reading the scdr. rese t clears the nf bit. 1 = noise detected 0 = no noise detected fe ? receiver framing error bit this clearable, read-only bit is set when a logic 0 is accepted as the stop bit. fe generates an sci error cpu interrupt request if the feie bit in scc3 also is set. clear the fe bit by reading scs1 with fe set and then reading the scdr. reset clears the fe bit. 1 = framing error detected 0 = no framing error detected
serial communications interface technical data mc68hc908ab32 ? rev. 1.1 272 serial communications interface module (sci) freescale semiconductor figure 15-13. fl ag clearing sequence pe ? receiver parity error bit this clearable, read-only bit is set when the sci detects a parity error in incoming data. pe generates a pe cpu interrupt request if the peie bit in scc3 is al so set. clear the pe bit by reading scs1 with pe set and then readi ng the scdr. reset clears the pe bit. 1 = parity error detected 0 = no parity error detected byte 1 normal flag clearing sequence read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 0 read scdr byte 2 scrf = 0 read scs1 scrf = 1 or = 0 scrf = 1 scrf = 0 read scdr byte 3 scrf = 0 byte 1 read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 1 read scdr byte 3 delayed flag clearing sequence or = 1 scrf = 1 or = 1 scrf = 0 or = 1 scrf = 0 or = 0
serial communications interface module (sci) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 273 15.9.5 sci status register 2 sci status register 2 co ntains flags to signal the following conditions: break character detected incoming data bkf ? break flag bit this clearable, read-only bit is set when the sci detects a break character on the pte1/rxd pin. in scs1, the fe and scrf bits are also set. in 9-bit ch aracter transmissions, t he r8 bit in scc3 is cleared. bkf does not generate a c pu interrupt request. clear bkf by reading scs2 with bkf set and then reading th e scdr. once cleared, bkf can become set again only after logic 1s again appear on the pte1/rxd pin followed by another break character. reset clears the bkf bit. 1 = break character detected 0 = no break ch aracter detected rpf ? reception in progress flag bit this read-only bit is set when the receiver detec ts a logic 0 during the rt1 time period of t he start bit search. rp f does not generate an interrupt request. rpf is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch) or when the receiver detects an idle character. pol ling rpf before disabling the sci module or entering stop mode can show whether a reception is in progress. 1 = reception in progress 0 = no reception in progress address: $0017 bit 7654321bit 0 read: bkf rpf write: reset:00000000 = unimplemented figure 15-14. sci status register 2 (scs2)
serial communications interface technical data mc68hc908ab32 ? rev. 1.1 274 serial communications interface module (sci) freescale semiconductor 15.9.6 sci data register the sci data register (scdr) is the buffer between the internal data bus and the receive and transmit shift r egisters. reset has no effect on data in the sci data register. r7/t7?r0/t0 ? receive/transmit data bits reading address $0018 accesses t he read-only received data bits, r7:r0. writing to ad dress $0018 writes the data to be transmitted, t7:t0. reset has no effect on the sci data register. note: do not use read/modify/write inst ructions on the sci data register. address: $0018 bit 7654321bit 0 read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 15-15. sci data register (scdr)
serial communications interface module (sci) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 275 15.9.7 sci baud rate register the baud rate register (scbr) selects the baud rate for bo th the receiver and the transmitter. scp1 and scp0 ? sci baud rate prescaler bits these read/write bits select the baud rate prescaler divisor as shown in table 15-6 . reset clears scp1 and scp0. scr2?scr0 ? sci baud rate select bits these read/write bits select the sc i baud rate divisor as shown in table 15-7 . reset clears scr2?scr0. address: $0019 bit 7654321bit 0 read: scp1 scp0 r scr2 scr1 scr0 write: reset:00000000 = unimplemented r = reserved figure 15-16. sci baud rate register (scbr) table 15-6. sci baud rate prescaling scp1 and scp0 prescaler divisor (pd) 00 1 01 3 10 4 11 13
serial communications interface technical data mc68hc908ab32 ? rev. 1.1 276 serial communications interface module (sci) freescale semiconductor use this formula to calc ulate the sci baud rate: where: sci clock source = cgmxclk (see 9.5.6 crystal output frequency signal (cgmxclk) .) pd = prescaler divisor bd = baud rate divisor this makes the formula: table 15-8 shows the sci baud rates that can be generated with a 4.9152mhz cgmxclk. table 15-7. sci baud rate selection scr2, scr1, and scr0 baud rate divisor (bd) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 baud rate sci clock source 64 pd bd ---------------- -------------- -------------- - = baud rate cgmxclk 64 pd bd -------------------- ---------------- =
serial communications interface module (sci) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial communications interface module (sci) 277 table 15-8. sci baud ra te selection examples scp1 and scp0 prescaler divisor (pd) scr2, scr1, and scr0 baud rate divisor (bd) baud rate (cgmxclk=4.9152 mhz) 00 1 000 1 76,800 00 1 001 2 38,400 00 1 010 4 19,200 00 1 011 8 9600 00 1 100 16 4800 00 1 101 32 2400 00 1 110 64 1200 00 1 111 128 600 01 3 000 1 25,600 01 3 001 2 12,800 01 3 010 4 6400 01 3 011 8 3200 01 3 100 16 1600 01 3 101 32 800 01 3 110 64 400 01 3 111 128 200 10 4 000 1 19,200 10 4 001 2 9600 10 4 010 4 4800 10 4 011 8 2400 10 4 100 16 1200 10 4 101 32 600 10 4 110 64 300 10 4 111 128 150 11 13 000 1 5908 11 13 001 2 2954 11 13 010 4 1477 11 13 011 8 739 11 13 100 16 369 11 13 101 32 185 11 13 110 64 92 11 13 111 128 46
serial communications interface technical data mc68hc908ab32 ? rev. 1.1 278 serial communications interface module (sci) freescale semiconductor
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial peripheral interface module (spi) 279 technical data ? mc68hc908ab32 section 16. serial peripheral interface module (spi) 16.1 contents 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 16.4 pin name conventions and i/o r egister addresses . . . . . . . 281 16.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 16.5.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 16.5.2 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 16.6 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285 16.6.1 clock phase and polarity controls. . . . . . . . . . . . . . . . . . . 285 16.6.2 transmission format wh en cpha = 0 . . . . . . . . . . . . . . . 286 16.6.3 transmission format wh en cpha = 1 . . . . . . . . . . . . . . . 288 16.6.4 transmission initiation latency . . . . . . . . . . . . . . . . . . . . . 289 16.7 queuing transmissi on data . . . . . . . . . . . . . . . . . . . . . . . . . . 291 16.8 error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 16.8.1 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 16.8.2 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 16.9 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 16.10 resetting the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 16.11 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 16.11.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299 16.11.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299 16.12 spi during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 300 16.13 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 16.13.1 miso (master in/slave out) . . . . . . . . . . . . . . . . . . . . . . . . 301 16.13.2 mosi (master out/slave in) . . . . . . . . . . . . . . . . . . . . . . . . 301
serial peripheral interface module (spi) technical data mc68hc908ab32 ? rev. 1.1 280 serial peripheral interface module (spi) freescale semiconductor 16.13.3 spsck (serial clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 16.13.4 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 16.13.5 cgnd (clock ground ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 16.14 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 16.14.1 spi control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 16.14.2 spi status and control register . . . . . . . . . . . . . . . . . . . . 306 16.14.3 spi data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 16.2 introduction this section describes th e serial peripheral in terface (spi) module, which allows full-duplex, synchr onous, serial communications with peripheral devices. 16.3 features features of the spi modu le include the following: full-duplex operation master and slave modes double-buffered operation with separate transmit and receive registers four master mode frequencie s (maximum = bus frequency 2) maximum slave mode frequency = bus frequency serial clock with program mable polarity and phase two separately enabled interrupts: ? sprf (spi receiver full) ? spte (spi transmitter empty) mode fault error flag wi th cpu interrupt capability overflow error flag with cpu interrupt capability programmable wired-or mode i 2 c (inter-integrated ci rcuit) compatibility i/o (input/output) port bit(s) soft ware configurab le with pullup device(s) if configured as input port bit(s)
serial peripheral interface module (spi) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial peripheral interface module (spi) 281 16.4 pin name convention s and i/o register addresses the text that follows describes t he spi. the spi i/o pin names are ss (slave select), spsck (spi serial clock), cgnd (c lock ground), mosi (master out slave in), and miso (master in/slave out). the spi shares four i/o pins with four parallel i/o ports. the full names of the spi i/o pins are shown in table 16-1 . the generic pin names appear in the text that follows. 16.5 functional description figure 16-1 summarizes the sp i i/o registers and figure 16-2 shows the structure of the spi module. table 16-1. pin name conventions spi generic pin names: miso mosi ss spsck cgnd full spi pin names: spi pte5/miso pte6/mosi pte4/ss pte7/spsck v ss addr.register name bit 7654321bit 0 $0010 spi control register (spcr) read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 $0011 spi status and control register (spscr) read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 $0012 spi data register (spdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset = unimplemented r = reserved figure 16-1. spi i/o register summary
serial peripheral interface module (spi) technical data mc68hc908ab32 ? rev. 1.1 282 serial peripheral interface module (spi) freescale semiconductor figure 16-2. spi module block diagram the spi module allows full-duplex, synchronous, serial communication between the mcu and peripheral devices, including other mcus. software can poll the spi status flags or spi opera tion can be interrupt- driven. the following paragraphs describe the operation of the spi module. transmitter cpu interrupt request reserved receiver/error cpu interrupt request 76543210 spr1 spmstr transmit data register shift register spr0 cgmout 2 clock select 2 clock divider 8 32 128 clock logic cpha cpol spi sprie r spe spwom sprf spte ovrf reserved m s pin control logic receive data register sptie spe internal bus from sim modfen errie control modf spmstr mosi miso spsck ss
serial peripheral interface module (spi) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial peripheral interface module (spi) 283 16.5.1 master mode the spi operates in mast er mode when the spi ma ster bit, spmstr, is set. note: configure the spi modul es as master or sl ave before enab ling them. enable the master spi before enabling the slave spi. disable the slave spi before disabling t he master spi. (see 16.14.1 spi control register .) only a master spi modul e can initiate transmi ssions. software begins the transmission from a master spi module by wr iting to t he transmit data register. if the shift register is empty, the by te immediately transfers to the shift register, setting the spi transmitter empty bit, spte. the byte begins shifting out on the mosi pin under the control of the serial clock. (see figure 16-3 .) figure 16-3. full-duplex master-slave connections shift register shift register baud rate generator master mcu slave mcu v dd mosi mosi miso miso spsck spsck ss ss
serial peripheral interface module (spi) technical data mc68hc908ab32 ? rev. 1.1 284 serial peripheral interface module (spi) freescale semiconductor the spr1 and spr0 bits control t he baud rate generator and determine the speed of the sh ift register. (see 16.14.2 spi stat us and control register .) through the spsck pin, the baud rate generator of the master also controls the shift register of the slave peripheral. as the byte shifts out on the mosi pin of the ma ster, another byte shifts in from the slave on the master?s miso pin. the transmission ends when the receiver full bit, sprf, becomes set. at t he same time that sprf becomes set, the byte from the slave transfers to the receive data register. in normal operation, spr f signals the end of a transmission. software clears sprf by reading the sp i status and contro l register with sprf set and then r eading the spi data registe r. writing to the spi data register clears the spte bit. 16.5.2 slave mode the spi operates in slave mode when t he spmstr bit is clear. in slave mode, the spsck pin is the input for the serial clock from the master mcu. before a data tr ansmission occurs, the ss pin of the slave spi must be at logic 0. ss must remain low unti l the transmission is complete. (see 16.8.2 mode fault error .) in a slave spi module, dat a enters the shift regist er under the control of the serial clock from the master spi module. after a byte enters the shift register of a slave spi, it transfers to the re ceive data regi ster, and the sprf bit is set. to prevent an over flow condition, slave software then must read the receive da ta register before anothe r full byte enters the shift register. the maximum frequency of the spsck for an spi configur ed as a slave is the bus clock speed (which is twic e as fast as the fastest master spsck clock that can be generat ed). the frequency of the spsck for an spi configured as a slave does not have to correspond to any spi baud rate. the baud rate only cont rols the speed of the spsck generated by an spi configured as a master. therefore, the frequency of the spsck for an spi configured as a slave can be any frequency less than or equal to the bus speed.
serial peripheral interface module (spi) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial peripheral interface module (spi) 285 when the master spi starts a transm ission, the data in the slave shift register begins shifting out on the miso pin. the sl ave can load its shift register with a new byte for the next transmission by writin g to its transmit data register. the slave must write to its transmit data register at least one bus cycle before the master star ts the next transmission. otherwise, the byte already in the slave shift register shif ts out on the miso pin. data written to the slav e shift register during a transmission remains in a buffer until the end of the transmission. when the clock phase bit (cpha) is set, the first edge of spsck starts a transmission. when cpha is clear, the falling edge of ss starts a transmission. (see 16.6 transmission formats .) note: spsck must be in the pr oper idle state before the slave is enabled to prevent spsck from appearing as a clock edge. 16.6 transmission formats during an spi transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). a serial clock synchronizes shifting and sampling on the two seri al data lines. a slave select line allows selection of an i ndividual slave spi device; slave devices that are not selected do not interfere with spi bus activities. on a master spi device, the slave select line can optional ly be used to i ndicate multiple- master bus contention. 16.6.1 clock phase and polarity controls software can select any of four co mbinations of seri al clock (spsck) phase and polarity using tw o bits in the spi cont rol register (spcr). the clock polarity is specified by the cpol control bit, which selects an active high or low clock and has no si gnificant effect on the transmission format.
serial peripheral interface module (spi) technical data mc68hc908ab32 ? rev. 1.1 286 serial peripheral interface module (spi) freescale semiconductor the clock phase (cpha) control bit se lects one of two fundamentally different transmission formats. the clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the phase an d polarity are changed between transmissions to allow a master devic e to communicate with peripheral slaves having diff erent requirements. note: before writing to the cp ol bit or the cpha bi t, disable the spi by clearing the spi enable bit (spe). 16.6.2 transmission format when cpha = 0 figure 16-4 shows an spi transmission in which cpha is logic 0. the figure should not be us ed as a replacement fo r data sheet parametric information. two waveforms are shown for s psck: one for cp ol = 0 and another for cpol = 1. the di agram may be interpreted as a master or slave timing diagram sinc e the serial clock (spsck) , master in/slave out (miso), and master out/slave in (m osi) pins are di rectly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the sl ave. the slave spi drives its miso output only when its slave select input (ss ) is at logic 0, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconf igured as general-purpose i/o not af fecting the spi. (see 16.8.2 mode fault error .) when cpha = 0, the first spsck edge is the msb capture st robe. therefore, the sl ave must begin driving its data before the fi rst spsck edge, and a fa lling edge on the ss pin is used to start the slave dat a transmission. the slave?s ss pin must be toggled back to high and then low agai n between each byte transmitted as shown in figure 16-5 .
serial peripheral interface module (spi) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial peripheral interface module (spi) 287 figure 16-4. transm ission format (cpha = 0) figure 16-5. cpha/ss timing when cpha = 0 for a slave, the falling edge of ss indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmit data register . therefore, the spi data register of the slave must be loaded with transmit dat a before the falling edge of ss . any data written after the falling edge is stor ed in the transmit data register and transferred to the shift register after the current transmission. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 12345678 spsck cycle # for reference spsck; cpol = 0 spsck; cpol =1 mosi from master miso from slave ss ; to slave capture strobe byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1
serial peripheral interface module (spi) technical data mc68hc908ab32 ? rev. 1.1 288 serial peripheral interface module (spi) freescale semiconductor 16.6.3 transmission format when cpha = 1 figure 16-6 shows an spi transmission in which cpha is logic 1. the figure should not be us ed as a replacement fo r data sheet parametric information. two wave forms are shown for s psck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock ( spsck), master in/slave out (miso), and master out/slave in (m osi) pins are directly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the sl ave. the slave spi drives its miso output only when its slave select input (ss ) is at logic 0, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconf igured as general-purpose i/o not af fecting the spi. (see 16.8.2 mode fault error .) when cpha = 1, the master begins driving its mosi pin on the first sps ck edge. therefore, the slave uses the first spsck edge as a start transmission signal. the ss pin can remain low between trans missions. this format may be preferable in systems hav ing only one master and only one slave driving the miso data line. figure 16-6. transm ission format (cpha = 1) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 12345678 spsck cycle # for reference spsck; cpol = 0 spsck; cpol =1 mosi from master miso from slave ss ; to slave capture strobe
serial peripheral interface module (spi) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial peripheral interface module (spi) 289 when cpha = 1 for a slav e, the first edge of the spsck indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmit data register . therefore, the spi data register of the slave must be loaded with transmit dat a before the first edge of spsck. any data written after the fi rst edge is stored in the transmit data register and transferred to the shift register after the current transmission. 16.6.4 transmission initiation latency when the spi is configured as a mast er (spmstr = 1), writing to the spdr starts a transmission . cpha has no ef fect on the delay to the start of the transmission, but it does affect the init ial state of the spsck signal. when cpha = 0, the spsck signal remains inactive for the first half of the first spsck cycle. when cpha = 1, the first spsck cycle begins with an edge on the spsck line from its inactive to its active level. the spi clock rate (selected by spr1:spr0) af fects the delay from the write to spd r and the start of t he spi transmission. (see figure 16-7 .) the internal spi clock in the master is a free-running derivative of the internal mcu clock. to conserve powe r, it is enabled only when both t he spe and spmstr bits are set. spsck edges occur halfway through the low time of the internal mcu cloc k. since the spi clock is free-running, it is uncertain where the write to the spdr occurs relative to the slower spsck. this uncertainty c auses the variation in the initiation delay shown in figure 16-7 . this delay is no longer than a single spi bit time. that is, the maximum delay is two mcu bus cycles for div2, eight mcu bus cycles for div8, 32 mcu bus cycles for div32, and 128 mcu bus cycl es for div128.
serial peripheral interface module (spi) technical data mc68hc908ab32 ? rev. 1.1 290 serial peripheral interface module (spi) freescale semiconductor figure 16-7. transmissi on start delay (master) write to spdr initiation delay bus mosi spsck cpha = 1 spsck cpha = 0 spsck cycle number msb bit 6 12 clock write to spdr earliest latest spsck = internal clock 2; earliest latest 2 possible start points spsck = internal clock 8; 8 possible start points earliest latest spsck = internal clock 32; 32 possible start points earliest latest spsck = internal clock 128; 128 possible start points write to spdr write to spdr write to spdr bus clock bit 5 3 bus clock bus clock bus clock ? ? ? initiation delay from write spdr to transfer begin
serial peripheral interface module (spi) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial peripheral interface module (spi) 291 16.7 queuing transmission data the double-buffered transmit data register allows a data byte to be queued and transmitted. for an spi configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. the sp i transmitter empty flag (spte) indicates when the transmit data buffer is ready to acce pt new data. write to the transmit data register only when the spte bit is high. figure 16-8 shows the timing associated with doi ng back-to-back transmi ssions with the spi (spsck has cpha: cpol = 1:0). figure 16-8. sprf/spte cpu interrupt timing the transmit data buffer allows back- to-back transmissions without the slave precisely timing its writes between transmissions as in a system with a single data buffer. also, if no new data is wr itten to the data buffer, the last value contained in the shift register is the next data word to be transmitted. bit 3 mosi spsck spte write to spdr 1 cpu writes byte 2 to spdr, queueing byte 2 cpu writes byte 1 to spdr, clearing spte bit. byte 1 transfers from transmit data 3 1 2 2 3 5 register to shift register, setting spte bit. sprf read spscr msb bit 6 bit 5 bit 4 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 byte 2 transfers from transmit data cpu writes byte 3 to spdr, queueing byte byte 3 transfers from transmit data 5 8 10 8 10 4 first incoming byte transfers from shift 6 cpu reads spscr with sprf bit set. 4 6 9 second incoming byte transfers from shift 9 11 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 3 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 12 cpu reads spdr, clearing sprf bit. bit 5 bit 4 byte 1 byte 2 byte 3 7 12 read spdr 7 cpu reads spdr, clearing sprf bit. 11 cpu reads spscr with sprf bit set. cpha:cpol = 1:0
serial peripheral interface module (spi) technical data mc68hc908ab32 ? rev. 1.1 292 serial peripheral interface module (spi) freescale semiconductor for an idle master or id le slave that has no dat a loaded into its transmit buffer, the spte is set again no more than two bus cycles after the transmit buffer empties in to the shift register. th is allows the user to queue up a 16-bit value to send. for an already active slave, the load of the shift register cannot occur until the transm ission is completed. this implies that a back-to-ba ck write to the transmit data register is not possible. the spte indicates when the next write can occur. 16.8 error conditions the following flags signal spi error conditions: overflow (ovrf) ? fai ling to read the spi data register before the next full byte ent ers the shift register sets the ovrf bit. the new byte does not transfer to the receive data register, and the unread byte still can be read. ovrf is in the spi status and control register. mode fault error (m odf) ? the modf bit indicates that the voltage on the slave select pin (ss ) is inconsistent with the mode of the spi. modf is in the sp i status and control register. 16.8.1 overflow error the overflow flag (ovrf) be comes set if the receiv e data register still has unread data from a previous trans mission when the capture strobe of bit 1 of the next tr ansmission occurs. the bit 1 capture strobe occurs in the middle of spsck cycle 7. (see figure 16-4 and figure 16-6 .) if an overflow occurs, all data received after the overflow and before the ovrf bit is cleared does not transfer to the re ceive data register and does not set the spi rece iver full bit (sprf). the unr ead data that transferred to the receive data register before t he overflow occurred can still be read. therefore, an overflow error always indica tes the loss of data. clear the overflow flag by reading the spi status and control register and then reading the spi data register. ovrf generates a receiv er/error cpu interrupt request if the error interrupt enable bit (err ie) is also set. the sprf, modf, and ovrf
serial peripheral interface module (spi) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial peripheral interface module (spi) 293 interrupts share the same cpu interrupt vector. (see figure 16-11 .) it is not possible to enabl e modf or ovrf indi vidually to generate a receiver/error cpu inte rrupt request. however, leaving modfen low prevents modf from being set. if the cpu sprf interr upt is enabled and the o vrf interrupt is not, watch for an over flow condition. figure 16-9 shows how it is possible to miss an overflow. the first part of figure 16-9 shows how it is possible to read the spscr and spdr to clear t he sprf without problems. however, as illustrated by the se cond transmission example, the ovrf bit can be set in between the ti me that spscr and spdr are read. figure 16-9. missed read of overflow condition in this case, an overflow can be missed easily. sinc e no more sprf interrupts can be generated until this ovrf is serv iced, it is not obvious that bytes are being lost as more transmissions are completed. to prevent this, either enabl e the ovrf interrupt or do another read of the spscr following the read of the spdr. this ens ures that the ovrf was not set before the sprf was clea red and that future transmissions can set the sprf bit. figure 16-10 illustrates this pr ocess. generally, to avoid this second spscr read, enable the ovrf to the cpu by setting the errie bit. read read ovrf sprf byte 1 byte 2 byte 3 byte 4 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, clearing sprf bit, byte 4 fails to set sprf bit because 1 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 clearing sprf bit. but not ovrf bit. ovrf bit is not cleared. byte 4 is lost. and ovrf bit clear. and ovrf bit clear. spscr spdr
serial peripheral interface module (spi) technical data mc68hc908ab32 ? rev. 1.1 294 serial peripheral interface module (spi) freescale semiconductor figure 16-10. clearing s prf when ovrf interr upt is not enabled 16.8.2 mode fault error setting the spmstr bit selects master mode and configures the spsck and mosi pins as output s and the miso pin as an input. clearing spmstr selects slave mode and configur es the spsck and mosi pins as inputs and the miso pin as an output. the mode fault bit, modf, becomes set any time the st ate of the slave select pin, ss , is inconsistent with the mode selected by spmstr. to prevent spi pin contention and damage to the mcu, a mode fault error occurs if: the ss pin of a slave spi goes high during a transmission the ss pin of a master spi goes low at any time for the modf flag to be set, the mode fault er ror enable bit (modfen) must be set. clearing th e modfen bit does not cl ear the modf flag but does prevent modf from being se t again after modf is cleared. read read ovrf sprf byte 1 byte 2 byte 3 byte 4 1 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, cpu reads spscr again byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, cpu reads spscr again cpu reads byte 2 spdr, byte 4 sets sprf bit. cpu reads spscr. cpu reads byte 4 in spdr, cpu reads spscr again 1 2 3 clearing sprf bit. 4 to check ovrf bit. 5 6 7 8 9 clearing sprf bit. to check ovrf bit. 10 clearing ovrf bit. 11 12 13 14 2 3 4 5 6 7 8 9 10 11 12 13 14 clearing sprf bit. to check ovrf bit. spi receive complete and ovrf bit clear. and ovrf bit clear. spscr spdr
serial peripheral interface module (spi) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial peripheral interface module (spi) 295 modf generates a receiver/error cp u interrupt request if the error interrupt enable bit (errie) is also set. t he sprf, modf, and ovrf interrupts share the same cpu interrupt vector. (see figure 16-11 .) it is not possible to enabl e modf or ovrf indi vidually to generate a receiver/error cpu inte rrupt request. however, leaving modfen low prevents modf from being set. in a master spi with th e mode fault enable bit (m odfen) set, the mode fault flag (modf) is set if ss goes to logic 0. a m ode fault in a master spi causes the following events to occur: if errie = 1, the spi generates an spi receiver/error cpu interrupt request. the spe bit is cleared. the spte bit is set. the spi state counter is cleared. the data direction regi ster of the shared i/o port regains control of port drivers. note: to prevent bus contention with another master spi after a mode fault error, clear all spi bits of the data direction regist er of the shared i/o port before enabling the spi. when configured as a slave (spmstr = 0), the modf fl ag is set if ss goes high during a trans mission. when cpha = 0, a transmission begins when ss goes low and ends once the in coming spsck goes back to its idle level following the shift of t he eighth data bit. w hen cpha = 1, the transmission begins when the sps ck leaves its idle level and ss is already low. the transmission continues until the spsck returns to its idle level following the shif t of the last data bit. (see 16.6 transmission formats .) note: setting the modf flag does not clear the spmstr bit. the spmstr bit has no function when spe = 0. reading spmstr when modf = 1 shows the difference between a modf occurring when the spi is a master and when it is a slave. when cpha = 0, a modf occurs if a slave is selected (ss is at logic 0) and later unselected (ss is at logic 1) even if no spsck is sent to that
serial peripheral interface module (spi) technical data mc68hc908ab32 ? rev. 1.1 296 serial peripheral interface module (spi) freescale semiconductor slave. this happens because ss at logic 0 indicate s the start of the transmission (miso driven out with the value of msb) for cpha = 0. when cpha = 1, a slave can be selected and then later unselected with no transmission occurri ng. therefore, modf does not occur since a transmission was never begun. in a slave spi (mstr = 0), t he modf bit generates an spi receiver/error cpu interr upt request if the errie bit is set. the modf bit does not clear th e spe bit or reset the spi in any way. software can abort the spi transmission by clear ing the spe bit of the slave. note: a logic 1 volt age on the ss pin of a slave spi puts the miso pin in a high impedance state. also, the slave spi ignores all incoming spsck clocks, even if it was already in the middle of a transmission. to clear the modf flag, read the sp scr with the modf bit set and then write to the spcr register. this ent ire clearing mechanism must occur with no modf condition existing or else the flag is not cleared. 16.9 interrupts four spi status flags can be enabled to generate cpu interrupt requests. table 16-2. spi interrupts flag request spte transmitter empty spi transmitter cpu interrupt request (sptie = 1, spe = 1) sprf receiver full spi receiver cpu interrupt request (sprie = 1) ovrf overflow spi receiver/error interrupt request (errie = 1) modf mode fault spi receiver/error interrupt request (errie = 1)
serial peripheral interface module (spi) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial peripheral interface module (spi) 297 reading the spi status and control register with sprf set and then reading the receive data register clears sprf. the clearing mechanism for the spte flag is always just a write to the trans mit data register. the spi transmitter inte rrupt enable bit (sptie ) enables the spte flag to generate transmitter cpu interrupt requests, pr ovided that the spi is enabled (spe = 1). the spi receiver interrupt enable bit (sprie) enables t he sprf bit to generate receiver cpu interrupt requests , regardless of the state of the spe bit. (see figure 16-11 .) the error interrupt enable bit (e rrie) enables both the modf and ovrf bits to generate a receiv er/error cpu in terrupt request. the mode fault enable bit (m odfen) can prevent t he modf flag from being set so that only the ovrf bit is enabled by the errie bit to generate receiver/error c pu interrupt requests. figure 16-11. sp i interrupt r equest generation spte sptie sprf sprie r errie modf ovrf spe cpu interrupt request cpu interrupt request not available spi transmitter not available spi receiver/error
serial peripheral interface module (spi) technical data mc68hc908ab32 ? rev. 1.1 298 serial peripheral interface module (spi) freescale semiconductor the following sources in the spi stat us and control register can generate cpu interrupt requests: spi receiver full bit (sprf) ? the sprf bit becomes set every time a byte transfers from the sh ift register to the receive data register. if the spi receiver interr upt enable bit, sprie, is also set, sprf generates an spi receiver /error cpu interrupt request. spi transmitter empty (spte) ? the spte bit becomes set every time a byte transfers from the tr ansmit data regist er to the shift register. if the spi trans mit interrupt enable bit, sptie, is also set, spte generates an spte cpu interrupt request. 16.10 resetting the spi any system reset completely resets the spi. partial resets occur whenever the spi enable bit (spe) is low. whenever spe is low, the following occurs: the spte flag is set. any transmission currently in progress is aborted. the shift register is cleared. the spi state counter is cleared, making it ready for a new complete transmission. all the spi port logi c is defaulted back to being general-purpose i/o. these items are reset only by a system reset: all control bits in the spcr register all control bits in the spscr register (modfen, errie, spr1, and spr0) the status flags sprf, ovrf, and modf by not resetting the control bits when spe is low, the user can clear spe between transmissions wit hout having to set all c ontrol bits again when spe is set back high fo r the next transmission.
serial peripheral interface module (spi) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial peripheral interface module (spi) 299 by not resetting the spr f, ovrf, and modf flags , the user can still service these interrupts after the spi has been disabl ed. the user can disable the spi by writing 0 to the spe bit. the spi can also be disabled by a mode fault occurring in an spi that was conf igured as a master with the modfen bit set. 16.11 low-power modes the wait and stop in structions put the mcu in low power- consumption standby modes. 16.11.1 wait mode the spi module remains active after the execution of a wait instruction. in wait mode the spi module registers are no t accessible by the cpu. any enabled cpu interrupt request from the spi module can bring the mcu out of wait mode. if spi module functions are not required during wait mode, reduce power consumption by disabl ing the spi module befor e executing the wait instruction. to exit wait mode when an overflow condition occurs, enable the ovrf bit to generate cpu interr upt requests by setti ng the error interrupt enable bit (err ie). (see 16.9 interrupts .) 16.11.2 stop mode the spi module is inactive after the execution of a st op instruction. the stop instruction does not affect register c onditions. spi operation resumes after an external interrupt. if stop mode is exited by reset, any transfer in progress is abor ted, and the spi is reset.
serial peripheral interface module (spi) technical data mc68hc908ab32 ? rev. 1.1 300 serial peripheral interface module (spi) freescale semiconductor 16.12 spi during break interrupts the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the sim break flag contro l register (sbfcr) enabl es software to clear status bits during t he break state. (see section 8. system integration module (sim) .) to allow software to clear status bi ts during a break interrupt, write a logic 1 to the bcfe bit. if a status bi t is cleared during t he break state, it remains cleared when the m cu exits the break state. to protect status bits du ring the break state, writ e a logic 0 to the bcfe bit. with bcfe at logic 0 (its defaul t state), software can read and write i/o registers during the break state wi thout affecting status bits. some status bits have a 2-st ep read/write clearing proced ure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. since the spte bit cannot be cleared during a break with the bcfe bit cleared, a write to the transmit data register in break mode does not initiate a transmission nor is this dat a transferred into th e shift register. therefore, a write to t he spdr in break mode with the bcfe bit cleared has no effect. 16.13 i/o signals the spi module has five i/o pins and shares four of them with a parallel i/o port. they are: miso ? data received mosi ? data transmitted spsck ? serial clock ss ? slave select cgnd ? clock ground (int ernally connected to v ss )
serial peripheral interface module (spi) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial peripheral interface module (spi) 301 the spi has limited inte r-integrated circuit (i 2 c) capability (requiring software support) as a master in a single-master environment. to communicate with i 2 c peripherals, mosi becom es an open-drain output when the spwom bit in the spi control regi ster is set. in i 2 c communication, the mo si and miso pins are connected to a bidirectional pin from the i 2 c peripheral and through a pullup resistor to v dd . 16.13.1 miso (master in/slave out) miso is one of the two spi module pins that transmits serial data. in full duplex operation, the miso pin of the mast er spi module is connected to the miso pin of the slave spi m odule. the master spi simultaneously receives data on its mi so pin and transmits dat a from its mosi pin. slave output data on the miso pin is enabl ed only when the spi is configured as a slave. the spi is configured as a slave when its spmstr bit is logic 0 and its ss pin is at logic 0. to support a multiple- slave system, a logic 1 on the ss pin puts the miso pin in a high- impedance state. when enabled, the spi controls dat a direction of the miso pin regardless of the state of the data direction regi ster of the shared i/o port. 16.13.2 mosi (master out/slave in) mosi is one of the two spi module pins that transmits serial data. in full- duplex operation, the mosi pin of the mast er spi module is connected to the mosi pin of the slave spi m odule. the master spi simultaneously transmits data from it s mosi pin and receives data on its miso pin. when enabled, the spi controls dat a direction of the mosi pin regardless of the state of the data direction regi ster of the shared i/o port.
serial peripheral interface module (spi) technical data mc68hc908ab32 ? rev. 1.1 302 serial peripheral interface module (spi) freescale semiconductor 16.13.3 spsck (serial clock) the serial clock synchronizes dat a transmission between master and slave devices. in a master mcu, the spsck pin is the cl ock output. in a slave mcu, the spsck pin is the clock input. in full-duplex operation, the master and slave mcus exchange a by te of data in eight serial clock cycles. when enabled, the spi controls dat a direction of the spsck pin regardless of the state of the data direction regi ster of the shared i/o port. 16.13.4 ss (slave select) the ss pin has various func tions depending on the cu rrent state of the spi. for an spi configur ed as a slave, the ss is used to select a slave. for cpha = 0, the ss is used to define the start of a transmission. (see 16.6 transmission formats .) since it is used to i ndicate the start of a transmission, the ss must be toggled high and low between each byte transmitted for the cpha = 0 format . however, it can remain low between transmissions for the cpha = 1 format. see figure 16-12 . figure 16-12. cpha/ss timing when an spi is configur ed as a slave, the ss pin is always configured as an input. it cannot be used as a general-purpose i/o regardless of the state of the modfen control bit. however, the modfen bit can still prevent the state of the ss from creating a modf error. (see 16.14.2 spi status and control register .) note: a logic 1 voltage on the ss pin of a slave spi puts the miso pin in a high- impedance state. the slave spi ignor es all incoming spsck clocks, even if it was already in t he middle of a transmission. byte 1 byte 3 miso/mosi byte 2 master ss slave ss cpha = 0 slave ss cpha = 1
serial peripheral interface module (spi) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial peripheral interface module (spi) 303 when an spi is configur ed as a master, the ss input can be used in conjunction with the modf flag to prevent multip le masters from driving mosi and spsck. (see 16.8.2 mode fault error .) for the state of the ss pin to set the modf flag, the modfen bit in the spsck register must be set. if the modfen bit is low for an spi master, the ss pin can be used as a general-purpo se i/o under the control of the data direction register of the shared i/o port. with modfen high, it is an input-only pin to the spi regardle ss of the state of the data direction regi ster of the shared i/o port. the cpu can always read the state of the ss pin by configuring the appropriate pin as an input and readi ng the port data register. (see table 16-3 .) 16.13.5 cgnd (clock ground) cgnd is the ground retu rn for the serial cl ock pin, spsck, and the ground for the port output buffers. it is inte rnally connected to v ss as shown in table 16-1 . table 16-3. spi configuration spe spmstr modfen spi configuration state of ss logic 0 x (1) x not enabled general-purpose i/o; ss ignored by spi 1 0 x slave input-only to spi 1 1 0 master without modf general-purpose i/o; ss ignored by spi 1 1 1 master with modf input-only to spi note 1. x = don?t care
serial peripheral interface module (spi) technical data mc68hc908ab32 ? rev. 1.1 304 serial peripheral interface module (spi) freescale semiconductor 16.14 i/o registers three registers control and monitor spi operation: spi control register (spcr) spi status and cont rol register (spscr) spi data register (spdr) 16.14.1 spi control register the spi control register: enables spi modul e interrupt requests configures the spi modul e as master or slave selects serial clock polarity and phase configures the spsck, mosi, and miso pins as open-drain outputs enables the spi module sprie ? spi receiver interrupt enable bit this read/write bi t enables cpu interrupt re quests generated by the sprf bit. the sprf bit is set when a byte transfers from the shift register to the receive data r egister. reset clear s the sprie bit. 1 = sprf cpu interr upt requests enabled 0 = sprf cpu interr upt requests disabled address: $0010 bit 7654321bit 0 read: sprie r spmstr cpol cpha spwom spe sptie write: reset:00101000 = unimplemented r = reserved figure 16-13. spi cont rol register (spcr)
serial peripheral interface module (spi) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial peripheral interface module (spi) 305 spmstr ? spi master bit this read/write bit sele cts master mode oper ation or slave mode operation. reset sets the spmstr bit. 1 = master mode 0 = slave mode cpol ? clock polarity bit this read/write bit det ermines the logic st ate of the spsck pin between transmissions. (see figure 16-4 and figure 16-6 .) to transmit data between spi modules, the spi modules must have identical cpol values. reset clears the cpol bit. cpha ? clock phase bit this read/write bit contro ls the timing relationship between the serial clock and spi data. (see figure 16-4 and figure 16-6 .) to transmit data between spi modules , the spi modules must have identical cpha values. when cpha = 0, the ss pin of the sl ave spi module must be set to logic 1 between bytes. (see figure 16-12 .) reset sets the cpha bit. spwom ? spi wired-or mode bit this read/write bit disa bles the pullup devices on pins spsck, mosi, and miso so that those pins become open-drain outputs. 1 = wired-or spsck, mosi, and miso pins 0 = normal push-pull sp sck, mosi, and miso pins spe ? spi enable this read/write bi t enables the spi module. clearing spe causes a partial reset of the spi. (see 16.10 resetting the spi .) reset clears the spe bit. 1 = spi module enabled 0 = spi module disabled sptie? spi transmit interrupt enable this read/write bi t enables cpu interrupt re quests generated by the spte bit. spte is set when a byte transfers fr om the transmit data register to the shif t register. reset cl ears the sptie bit. 1 = spte cpu interr upt requests enabled 0 = spte cpu interr upt requests disabled
serial peripheral interface module (spi) technical data mc68hc908ab32 ? rev. 1.1 306 serial peripheral interface module (spi) freescale semiconductor 16.14.2 spi status and control register the spi status and control register contains flags to signal these conditions: receive data register full failure to clear sprf bit before next byte is received (overflow error) inconsistent logic level on ss pin (mode fault error) transmit data r egister empty the spi status and control r egister also contains bi ts that perform these functions: enable error interrupts enable mode fault error detection select master spi baud rate sprf ? spi receiver full bit this clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. sprf generates a cpu interrupt request if the s prie bit in the spi contro l register is set also. during an sprf cpu interrupt, the cpu clears sprf by reading the spi status and control register wi th sprf set and then reading the spi data register. rese t clears the sprf bit. 1 = receive data register full 0 = receive data register not full address: $0011 bit 7654321bit 0 read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset:00001000 = unimplemented figure 16-14. spi status an d control register (spscr)
serial peripheral interface module (spi) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial peripheral interface module (spi) 307 errie ? error interrupt enable bit this read/write bit enabl es the modf and ovrf bits to generate cpu interrupt requests. re set clears t he errie bit. 1 = modf and ovrf can generat e cpu interrupt requests 0 = modf and ovrf cannot gener ate cpu interrupt requests ovrf ? overflow bit this clearable, read- only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register. in an overflow condition, th e byte already in the receive data register is unaffected, and t he byte that shifted in last is lost. clear the ovrf bit by reading the spi status and control register with ovrf set and then reading the receive data regi ster. reset clears the ovrf bit. 1 = overflow 0 = no overflow modf ? mode fault bit this clearable, read-only flag is set in a slave spi if the ss pin goes high during a transmission with the modfen bit set. in a master spi, the modf flag is set if the ss pin goes low at any time with the modfen bit set. clear the modf bi t by reading the spi status and control register (sp scr) with modf set and t hen writing to the spi control register (spcr). reset clears the modf bit. 1 = ss pin at inappropriate logic level 0 = ss pin at appropria te logic level spte ? spi transmi tter empty bit this clearable, read-only flag is set each time t he transmit data register transfers a by te into the shift regi ster. spte generates an spte cpu interrupt request if the sptie bit in t he spi contro l register is set also. note: do not write to the spi data r egister unless the spte bit is high. during an spte cpu in terrupt, the cpu clear s the spte bit by writing to the transmit data register. reset sets the spte bit. 1 = transmit data register empty 0 = transmit data r egister not empty
serial peripheral interface module (spi) technical data mc68hc908ab32 ? rev. 1.1 308 serial peripheral interface module (spi) freescale semiconductor modfen ? mode fault enable bit this read/write bit, when set to 1, allows the modf flag to be set. if the modf flag is set, clearing the modfen does not clear the modf flag. if the spi is enabled as a master and the modfen bit is low, then the ss pin is available as a general-purpose i/o. if the modfen bit is set, then this pin is not avail able as a general- purpose i/o. when t he spi is enabled as a slave, the ss pin is not available as a general-purpose i/ o regardless of the value of modfen. (see 16.13.4 ss (sl ave select) .) if the modfen bit is lo w, the level of the ss pin does not affect the operation of an enabled spi config ured as a master. for an enabled spi configured as a slave, havin g modfen low only prevents the modf flag from being se t. it does not affect any other part of spi operation. (see 16.8.2 mode fault error .) spr1 and spr0 ? spi baud rate select bits in master mode, these read/write bits select one of four baud rates as shown in table 16-4 . spr1 and spr0 have no effect in slave mode. reset clears spr1 and spr0. use this formula to calc ulate the spi baud rate: where: cgmout = base clock output of the clock generator module (cgm) bd = baud rate divisor table 16-4. spi master baud rate selection spr1 and spr0 baud rate divisor (bd) 00 2 01 8 10 32 11 128 baud rate cgmout 2bd -------------- ------------ =
serial peripheral interface module (spi) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor serial peripheral interface module (spi) 309 16.14.3 spi data register the spi data register consists of t he read-only receive data register and the write-only transmit data register . writing to the spi data register writes data into the transmit data r egister. reading the spi data register reads data from the rece ive data register. the tr ansmit data and receive data registers are separat e registers that can c ontain different values. (see figure 16-2 .) r7?r0/t7?t0 ? receive/ transmit data bits note: do not use read-modi fy-write instructions on t he spi data register since the register read is not the same as th e register written. address: $0012 bit 7654321bit 0 read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 16-15. spi data register (spdr)
serial peripheral interface module (spi) technical data mc68hc908ab32 ? rev. 1.1 310 serial peripheral interface module (spi) freescale semiconductor
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 311 technical data ? mc68hc908ab32 section 17. input/output (i/o) ports 17.1 contents 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 17.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 17.3.1 port a data register (pta) . . . . . . . . . . . . . . . . . . . . . . . . 316 17.3.2 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . 316 17.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 17.4.1 port b data register (ptb) . . . . . . . . . . . . . . . . . . . . . . . . 318 17.4.2 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . 319 17.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 17.5.1 port c data register (ptc) . . . . . . . . . . . . . . . . . . . . . . . . 320 17.5.2 data direction register c (ddrc). . . . . . . . . . . . . . . . . . . 321 17.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 17.6.1 port d data register (ptd) . . . . . . . . . . . . . . . . . . . . . . . . 323 17.6.2 data direction register d (ddrd). . . . . . . . . . . . . . . . . . . 324 17.6.3 port d input pullup enable register (ptdp ue). . . . . . . . . 325 17.7 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 17.7.1 port e data register (pte) . . . . . . . . . . . . . . . . . . . . . . . . 326 17.7.2 data direction register e (ddre) . . . . . . . . . . . . . . . . . . . 328 17.8 port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 17.8.1 port f data register (ptf) . . . . . . . . . . . . . . . . . . . . . . . . 329 17.8.2 data direction register f (ddrf) . . . . . . . . . . . . . . . . . . . 330 17.8.3 port f input pullup enable regi ster (ptfpue) . . . . . . . . . 332 17.9 port g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 17.9.1 port g data register (ptg) . . . . . . . . . . . . . . . . . . . . . . . . 332 17.9.2 data direction register g (ddrg) . . . . . . . . . . . . . . . . . . 333 17.10 port h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 17.10.1 port h data register (pth) . . . . . . . . . . . . . . . . . . . . . . . . 335 17.10.2 data direction register h (ddrh). . . . . . . . . . . . . . . . . . . 335
input/output (i/o) ports technical data mc68hc908ab32 ? rev. 1.1 312 input/output (i/o) ports freescale semiconductor 17.2 introduction fifty-one bidirectional inpu t-output (i/o) pins form eight parallel ports. all i/o pins are programmab le as inputs or outputs. note: connect any unused i/o pins to an appr opriate logic level, either v dd or v ss . although the i/o port s do not require te rmination for proper operation, termination reduces e xcess current consumption and the possibility of el ectrostatic damage. addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) read: 0 0 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) read: mclken 0 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 figure 17-1. i/o port register summary
input/output (i/o) ports mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 313 $0008 port e data register (pte) read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0009 port f data register (ptf) read: ptf7 ptf6 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 write: reset: unaffected by reset $000a port g data register (ptg) read: 00000 ptg2 ptg1 ptg0 write: reset: unaffected by reset $000b port h data register (pth) read: 000000 pth1 pth0 write: reset: unaffected by reset $000c data direction register e (ddre) read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 $000d data direction register f (ddrf) read: ddrf7 ddrf6 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: reset:00000000 $000e data direction register g (ddrg) read: 00000 ddrg2 ddrg1 ddrg0 write: reset:00000000 $000f data direction register h (ddrh) read: 000000 ddrh1 ddrh0 write: reset:00000000 $003d port d input pullup enable register (ptdpue) read: ptdpue7 ptdpue6 ptdpue5 ptdpue4 ptdpue3 ptdpue2 ptdpue1 ptdpue0 write: reset:00000000 $003e port f input pullup enable register (ptfpue) read: ptfpue7 ptfpue6 ptfpue5 ptfpue4 ptfpue3 ptfpue2 ptfpue1 ptfpue0 write: reset:00000000 addr.register name bit 7654321bit 0 figure 17-1. i/o port register summary
input/output (i/o) ports technical data mc68hc908ab32 ? rev. 1.1 314 input/output (i/o) ports freescale semiconductor table 17-1. port control regist er bits summary (sheet 1 of 2) port bit ddr module control pin module register control bit a 0 ddra0 ??? pta0 1 ddra1 pta1 2 ddra2 pta2 3 ddra3 pta3 4 ddra4 pta4 5 ddra5 pta5 6 ddra6 pta6 7 ddra7 pta7 b 0 ddrb0 adc adscr $0038 adch[4:0] ptb0/atd0 1 ddrb1 ptb1/atd1 2 ddrb2 ptb2/atd2 3 ddrb3 ptb3/atd3 4 ddrb4 ptb4/atd4 5 ddrb5 ptb5/atd5 6 ddrb6 ptb6/atd6 7 ddrb7 ptb7/atd7 c 0 ddrc0 ??? ptc0 1 ddrc1 ptc1 2 ddrc2 ? ddrc $0006 mclken ptc2/mclk 3 ddrc3 ?? ? ptc3 4 ddrc4 ptc4 5 ddrc5 ptc5 d 0 ddrd0 ??? ptd0 1 ddrd1 ptd1 2 ddrd2 ptd2 3 ddrd3 ptd3 4 ddrd4 timb tbsc $0040 ps[2:0] ptd4/tbclk 5 ddrd5 ? ? ? ptd5 6 ddrd6 tima tasc $0020 ps[2:0] ptd6/taclk 7 ddrd7 ? ? ? ptd7
input/output (i/o) ports mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 315 e 0 ddre0 sci scc1 $0013 ensci pte0/txd 1 ddre1 pte1/rxd 2 ddre2 tima ta s c 0 $0026 els0b:els0a pte2/tach0 3 ddre3 ta s c 1 $0029 els1b:els1a pte3/tach1 4 ddre4 spi spcr $0010 spe, spmstr pte4/ss 5 ddre5 spe pte5/miso 6 ddre6 pte6/mosi 7 ddre7 pte7spsck f 0 ddrf0 tima ta s c 2 $002c els2b:els2a ptf0/tach2 1 ddrf1 ta s c 3 $002f els3b:els3a ptf1/tach3 2 ddrf2 timb tbsc2 $0032 els2b:els2a ptf2/tbch2 3 ddrf3 tbsc3 $0035 els3b:els3a ptf3/tbch3 4 ddrf4 tbsc0 $0045 els0b:els0a ptf4/tbch0 5 ddrf5 tbsc1 $0048 els1b:els1a ptf5/tbch1 6 ddrf6 ??? ptf6 7 ddrf7 ptf7 g 0 ddrg0 kbi kbier $0021 kbie0 ptg0/kbd0 1 ddrg1 kbie1 ptg1/kbd1 2 ddrg2 kbie2 ptg2/kbd2 h 0 ddrh0 kbie3 pth0/kbd3 1 ddrh1 kbie4 pth1/kbd4 table 17-1. port control regist er bits summary (sheet 2 of 2) port bit ddr module control pin module register control bit
input/output (i/o) ports technical data mc68hc908ab32 ? rev. 1.1 316 input/output (i/o) ports freescale semiconductor 17.3 port a port a is an 8-bit general-pur pose bidirectional i/o port. 17.3.1 port a data register (pta) the port a data regist er contains a data latch fo r each of the eight port a pins. pta[7:0] ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. 17.3.2 data direction register a (ddra) data direction register a determine s whether each port a pin is an input or an output. writing a logic 1 to a ddra bit enables t he output buffer for the corresponding port a pin; a logi c 0 disables the output buffer. address: $0000 bit 7654321bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset figure 17-2. port a data register (pta) address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 17-3. data dir ection register a (ddra)
input/output (i/o) ports mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 317 ddra[7:0] ? data dire ction register a bits these read/write bits control port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pi ns by writing to the port a data register before changing data direction register a bits from 0 to 1. figure 17-4 shows the port a i/o logic. figure 17-4. port a i/o circuit when ddrax is a logic 1, readi ng address $0000 reads the ptax data latch. when ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data la tch can always be written, regardless of the state of its data direction bit. table 17-2 summarizes the operat ion of the port a pins. table 17-2. port a pin functions ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 0x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddra[7:0] pin pta[7:0] (3) 3. writing affects data regist er, but does not affect input. 1 x output ddra[7:0] pta[7:0] pta[7:0] read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus
input/output (i/o) ports technical data mc68hc908ab32 ? rev. 1.1 318 input/output (i/o) ports freescale semiconductor 17.4 port b port b is an 8-bit special function port th at shares all eight of its port pins with the analog-to-digital converter (adc) module (see section 14. analog-to-digital converter (adc) ). 17.4.1 port b data register (ptb) the port b data register co ntains a data latch for each of the eight port b pins. ptb[7:0] ? port b data bits these read/write bits are software programmable. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. atd[7:0] ? adc channels atd[7:0] are pins used for the input channels to the analog-to-digital converter module. the channel sele ct bits in the adc status and control register define which port b pin will be used as an adc input and overrides any control fr om the port i/o logic by forcing that pin as the input to the analog circuitry. note: care must be taken when reading port b while applyin g analog voltages to atd[7:0] pins. if the appropriate adc channel is not enabled, excessive current drain may occur if analog voltages are applied to the ptbx/atdx pin, while pt b is read as a digita l input. those ports not selected as analog input channels are considered digital i/o ports. address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset alternative function: atd7 at d6 atd5 atd4 atd3 atd2 atd2 atd0 figure 17-5. port b data register (ptb)
input/output (i/o) ports mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 319 17.4.2 data direction register b (ddrb) data direction register b determine s whether each port b pin is an input or an output. writing a logic 1 to a ddrb bit enables t he output buffer for the corresponding port b pin; a logi c 0 disables the output buffer. ddrb[7:0] ? data dire ction register b bits these read/write bits control port b data direction. reset clears ddrb[7:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pi ns by writing to the port b data register before changing data direction register b bits from 0 to 1. figure 17-7 shows the port b i/o logic. figure 17-7. port b i/o circuit address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 17-6. data dir ection register b (ddrb) read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus to analog-to-digital converter
input/output (i/o) ports technical data mc68hc908ab32 ? rev. 1.1 320 input/output (i/o) ports freescale semiconductor when ddrbx is a logic 1, readi ng address $0001 reads the ptbx data latch. when ddrbx is a logic 0, reading address $0001 reads the voltage level on the pin. the data la tch can always be written, regardless of the state of its data direction bit. table 17-3 summarizes the operat ion of the port b pins. 17.5 port c port c is a 6-bit general- purpose bidirectional i/o port. ptc2 pin can be configured as an output pi n for the system mclk clock. 17.5.1 port c data register (ptc) the port c data regist er contains a data latch fo r each of t he six port c pins. table 17-3. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddrb[7:0] pin ptb[7:0] (3) 3. writing affects data regist er, but does not affect input. 1 x output ddrb[7:0] ptb[7:0] ptb[7:0] address: $0002 bit 7654321bit 0 read: 0 0 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset alternative function: mclk figure 17-8. port c data register (ptc)
input/output (i/o) ports mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 321 ptc[5:0] ? port c data bits these read/write bits are software programmable. data direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. mclk ? t12 system clock the system clock is driven out of t he ptc2 pin when mclken is set. 17.5.2 data direction register c (ddrc) data direction register c determines whether eac h port c pin is an input or an output. writing a logic 1 to a ddrc bit enables the output buffer for the corresponding port c pin; a logi c 0 disables the output buffer. mclken ? t12 system clock enable bit this read/write bit enables mclk to be an ou tput signal on ptc2 pin. reset clears mclken. 1 = ptc2 pin confi gured as mclk output 0 = ptc2 pin configur ed as standard i/o pin ddrc[5:0] ? data dire ction register c bits these read/write bits control port c data direction. reset clears ddrc[5:0], configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note: avoid glitches on port c pins by writ ing to the port c dat a register before changing data direction register c bits from 0 to 1. figure 17-10 shows the port c i/o logic. address: $0006 bit 7654321bit 0 read: mclken 0 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 figure 17-9. data dir ection register b (ddrb)
input/output (i/o) ports technical data mc68hc908ab32 ? rev. 1.1 322 input/output (i/o) ports freescale semiconductor figure 17-10. port c i/o circuit when ddrcx is a logic 1, reading address $0002 reads the ptcx data latch. when ddrcx is a logic 0, reading address $0002 reads the voltage level on the pin. the data la tch can always be written, regardless of the state of its data direction bit. table 17-4 summarizes the operat ion of the port c pins. table 17-4. port c pin functions ddrc bit ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write 0 2 input, hi-z ddrc7 pin ptc2 1 2 output ddrc7 0 ? 0x (1) notes : 1. x = don?t care; except ptc2. input, hi-z (2) 2. hi-z = high impedance. ddrc[5:0] pin ptc[5:0] (3) 3. writing affects data regist er, but does not affect input. 1 x output ddrc[5:0] ptc[5:0] ptc[5:0] read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus mclk mclken ptc2 only
input/output (i/o) ports mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 323 17.6 port d port d is an 8-bit special function port that shares two of its pins with the timer interface module (see section 11. timer interface module a (tima) and section 12. timer inte rface module b (timb) ). each port d pin has 15ma cu rrent drive (sink) and programmable pullup. 17.6.1 port d data register (ptd) the port d data register c ontains a data latch for each of the eight port d pins. ptd[7:0] ? port d data bits these read/write bits are software programmable. data direction of each port d pin is under the control of the corresponding bit in data direction register d. reset has no effect on port d data. taclk ? timer a clock input the ptd6 pin becomes taclk, the timer a (tima) external clock input when the tima prescaler select bits, ps [2:0] = 111. see section 11. timer interface module a (tima) . tbclk ? timer b clock input the ptd4 pin becomes tbclk, the timer b (timb) external clock input when the timb prescaler select bits, ps [2:0] = 111. see section 12. timer interface module b (timb) . address: $0003 bit 7654321bit 0 read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset alternative function: taclk tbclk additional functions: 15ma sink 15ma sink 15ma sink 15ma sink 15ma sink 15ma sink 15ma sink 15ma sink input pullup input pullup input pullup input pullup input pullup input pullup input pullup input pullup figure 17-11. port d data register (ptd)
input/output (i/o) ports technical data mc68hc908ab32 ? rev. 1.1 324 input/output (i/o) ports freescale semiconductor 17.6.2 data direction register d (ddrd) data direction register d determines whether eac h port d pin is an input or an output. writing a logic 1 to a ddrd bit enables the output buffer for the corresponding port d pin; a logi c 0 disables the output buffer. ddrd[7:0] ? data dire ction register d bits these read/write bits control port d data direction. reset clears ddrd[7:0], configuring all port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input note: avoid glitches on port d pins by writ ing to the port d dat a register before changing data direction register d bits from 0 to 1. figure 17-13 shows the port d i/o logic. figure 17-13. port d i/o circuit address: $0007 bit 7654321bit 0 read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 figure 17-12. data dir ection register d (ddrd) read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptdx ddrdx ptdx internal data bus ptdpuex ptd6 to taclk of tima ptd4 to tbclk of timb v dd
input/output (i/o) ports mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 325 when ddrdx is a logic 1, reading address $0003 reads the ptdx data latch. when ddrdx is a logic 0, reading address $0003 reads the voltage level on the pin. the data la tch can always be written, regardless of the state of its data direction bit. table 17-5 summarizes the operat ion of the port d pins. 17.6.3 port d input pullup enable register (ptdpue) the port d input pullup enabl e register (ptdpue) controls the input pullup device for each of the eight port d pins. each bit is individually configurable and requires that the data directi on register, ddrd, bit be configured as an input. each pullup is automatically and dynamically disabled when a port bit?s ddrd is configured for output mode. ptdpue[7:0] ? port d input pullup enable bits these writable bits are software programmable to enable pullup devices on an input port pin. 1 = corresponding port d pin conf igured to have internal pullup 0 = corresponding port d pin internal pullup disconnected table 17-5. port d pin functions ddrd bit ptd bit i/o pin mode accesses to ddrd accesses to ptd read/write read write 0x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddrd[7:0] pin ptd[7:0] (3) 3. writing affects data register, but does not affect the input. 1 x output ddrd[7:0] ptd[7:0] ptd[7:0] address: $003d bit 7654321bit 0 read: ptdpue7 ptdpue6 ptdpue5 ptdpue4 ptdpue3 ptdpue2 ptdpue1 ptdpue0 write: reset:00000000 figure 17-14. port d input pu llup enable register (ptdpue)
input/output (i/o) ports technical data mc68hc908ab32 ? rev. 1.1 326 input/output (i/o) ports freescale semiconductor 17.7 port e port e is an 8-bit special function port t hat shares two of its pins with the timer interface module (tima), tw o of its pins wi th the serial communications interface module (s ci) and four of its pins with the serial peripheral interface module (spi). 17.7.1 port e data register (pte) the port e data register co ntains a data latch for each of the eight port e pins. pte[7:0] ? port e data bits these read/write bits are software programmable. data direction of each port e pin is under the control of the corresponding bit in data direction register e. reset has no effect on port e data. spsck ? spi se rial clock the pte7/spsck pin is the serial clock input of a spi slave module and serial clock output of a spi master modules . when the spe bit is clear, the pte7/spsck pin is av ailable for general -purpose i/o. see 16.14.1 spi control register . mosi ? master out/slave in the pte6/mosi pin is the master out /slave in terminal of the spi module. when the spe bit is clear, the pte6/m osi pin is available for general-purpose i /o. see 16.14.1 spi control register . address: $0008 bit 7654321bit 0 read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset alternative function: spsck mosi miso ss tach1 tach0 rxd txd figure 17-15. port e data register (pte)
input/output (i/o) ports mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 327 miso ? master in/slave out the pte5/miso pin is the master in /slave out termi nal of the spi module. when the spi enable bit, spe, is clear, the spi module is disabled, and the pte5/miso pin is available for general-purpose i/o. see 16.14.1 spi control register . ss ? slave select the pte4/ss pin is the slave select in put of the spi module. when the spe bit is clear, or when the spi mast er bit, spmstr, is set, the pte4/ss pin is available for general-purpose i/o. see 16.14.1 spi control register . when the spi is enabled as a slave, the ddre4 bit in data direction register e (ddre) has no effect on the pte4/ss pin. tach[1:0] ? timer a channel i/o bits the pte3/tach1?pte2/ tach0 pins are the tima input capture/output compare pins. the edge/level select bits, elsxb:elsxa, determine whet her the pte3/tach1?pte2/tach0 pins are timer channel i/o pins or general- purpose i/o pins. see 11.10.4 tima channel stat us and control registers . rxd ? sci receive data input the pte1/rxd pin is the receive dat a input for the sci module. when the enable sci bit, ensci, is clear, the sci module is disabled, and the pte1/rxd pin is availabl e for general-purpose i/o. see 15.9.1 sci control register 1 . txd ? sci transmit data output the pte0/txd pin is the transmit data output for the sci module. when the enable sci bit, ensci, is clear, the sc i module is disabled, and the pte0/txd pin is availabl e for general-pur pose i/o. see 15.9.1 sci contro l register 1 . note: data direction register e (ddre) does not affect the data direction of port e pins that are being used by the spi module, tima, and sci module. however, the ddre bits always determine whether reading port e returns the states of the latc hes or the states of the pins. see table 17-6 .
input/output (i/o) ports technical data mc68hc908ab32 ? rev. 1.1 328 input/output (i/o) ports freescale semiconductor 17.7.2 data direction register e (ddre) data direction register e determine s whether each port e pin is an input or an output. writing a logic 1 to a ddre bit enables t he output buffer for the corresponding port e pin; a logi c 0 disables the output buffer. ddre[7:0] ? data dire ction register e bits these read/write bits control port e data direction. reset clears ddre[7:0], configuring all port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input note: avoid glitches on port e pi ns by writing to the port e data register before changing data direction register e bits from 0 to 1. figure 17-17 shows the port e i/o logic. figure 17-17. port e i/o circuit address: $000c bit 7654321bit 0 read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 figure 17-16. data dir ection register e (ddre) read ddre ($000c) write ddre ($000c) reset write pte ($0008) read pte ($0008) ptex ddrex ptex internal data bus
input/output (i/o) ports mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 329 when ddrex is a logic 1, readi ng address $0008 reads the ptex data latch. when ddrex is a logic 0, reading address $0008 reads the voltage level on the pin. the data la tch can always be written, regardless of the state of its data direction bit. table 17-6 summarizes the operat ion of the port e pins. 17.8 port f port f is an 8-bit special function port that shares six of its pins with the timer interface modules (tima and timb). 17.8.1 port f data register (ptf) the port f data register contains a data latch for each of the eight port f pins. table 17-6. port e pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to pte read/write read write 0x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddre[7:0] pin pte[7:0] (3) 3. writing affects data register, but does not affect the input. 1 x output ddre[7:0] pte[7:0] pte[7:0] address: $0009 bit 7654321bit 0 read: ptf7 ptf6 ptf5 ptf4 ptf3 ptf2 ptf1 ptf0 write: reset: unaffected by reset alternative function: tbch1 tbch0 tbch3 tbch2 tach3 tach2 additional function: input pullup input pullup input pullup input pullup input pullup input pullup input pullup input pullup figure 17-18. port f data register (ptf)
input/output (i/o) ports technical data mc68hc908ab32 ? rev. 1.1 330 input/output (i/o) ports freescale semiconductor ptf[7:0] ? port f data bits these read/write bits are software programmable. data direction of each port f pin is under the control of the correspondi ng bit in data direction register f. rese t has no effect on port f data. tach[3:2] and tbch[3:0] ? timer channel i/o bits the ptf5/tbch1?ptf0/tach2 pins are the tima and timb input capture/output compare pins. the edge/level select bits, elsxb:elsxa, determine whet her the ptf5/t bch1?ptf0/tach2 pins are timer channel i/o pins or general- purpose i/o pins. see 11.10.4 tima channel stat us and control registers and 12.10.4 timb channel status and control registers . note: data direction register f (ddrf) does not affect the data direction of port f pins that are being used by ti ma and timb. howe ver, the ddrf bits always determine w hether reading port f retu rns the states of the latches or the states of the pins. see table 17-7 . 17.8.2 data direction register f (ddrf) data direction register f determines whether each port f pin is an input or an output. writing a l ogic 1 to a ddrf bit enables the output buffer for the corresponding port f pin; a logi c 0 disables the output buffer. ddrf[7:0] ? data direction register f bits these read/write bits control port f data direction. reset clears ddrf[7:0], configuring a ll port f pins as inputs. 1 = corresponding port f pi n configured as output 0 = corresponding port f pi n configured as input address: $000d bit 7654321bit 0 read: ddrf7 ddrf6 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: reset:00000000 figure 17-19. data direct ion register f (ddrf)
input/output (i/o) ports mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 331 note: avoid glitches on port f pins by writ ing to the port f dat a register before changing data direction register f bits from 0 to 1. figure 17-20 shows the port f i/o logic. figure 17-20. port f i/o circuit when ddrfx is a logic 1, reading addre ss $0009 reads the ptfx data latch. when ddrfx is a logic 0, reading address $0009 reads the voltage level on the pin. the data la tch can always be written, regardless of the state of its data direction bit. table 17-7 summarizes the operat ion of the port f pins. table 17-7. port f pin functions ddrf bit ptf bit i/o pin mode accesses to ddrf accesses to ptf read/write read write 0x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddrf[7:0] pin ptf[7:0] (3) 3. writing affects data register, but does not affect the input. 1 x output ddrf[7:0] ptf[7:0] ptf[7:0] read ddrf ($000d) write ddrf ($000d) reset write ptf ($0009) read ptf ($0009) ptfx ddrfx ptfx internal data bus ptf5 to tbch1, ptf4 to tbch0, ptf3 to tbch3, ptf2 to tbch2 of timb ptf1 to tach3, ptf0 to tach2 of tima ptfpuex v dd
input/output (i/o) ports technical data mc68hc908ab32 ? rev. 1.1 332 input/output (i/o) ports freescale semiconductor 17.8.3 port f input pullup enable register (ptfpue) the port f input pullup e nable register (ptfpue) controls the input pullup device for each of the eight por t f pins. each bi t is individually configurable and requi res that the data directi on register, ddrf, bit be configured as an input. each pullup is automatically and dynamically disabled when a port bit?s ddrf is configured for output mode. ptfpue[7:0] ? port f input pullup enable bits these writable bits are software programmable to enable pullup devices on an input port pin. 1 = corresponding port f pin confi gured to have internal pullup 0 = corresponding port f pin internal pullup disconnected 17.9 port g port g is a 3-bit special-f unction port that shares al l three of its pins with the keyboard interrupt (kbi) module. 17.9.1 port g data register (ptg) the port g data regist er (ptg) contains a data la tch for each of the three port g pins. address: $003e bit 7654321bit 0 read: ptfpue7 ptfpue6 ptfpue5 ptfpue4 p tfpue3 ptfpue2 p tfpue1 ptfpue0 write: reset:00000000 figure 17-21. port f input pullup enabl e register (ptfpue)
input/output (i/o) ports mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 333 ptg[2:0] ? port g data bits these read/write bits are software programmable. data direction of each port g pin is under the control of the corresponding bit in data direction register g. reset ha s no effect on port g data. kbd[2:0] ? the keyboard interrupt enable bits, kbie[2:0], in the keyboard interrupt enable register (kbier ), enable the port g pins as external interrupt pins. see section 19. keyboard interrupt module (kbi) . 17.9.2 data direction register g (ddrg) data direction regi ster g determines whether each port g pin is an input or an output. writing logi c 1 to a ddrg bit enables the out put buffer for the corresponding port g pin; a lo gic 0 disables the output buffer. address: $000a bit 7654321bit 0 read: 0 0 0 0 0 ptg2 ptg1 ptg0 write: reset: unaffected by reset alternative function: kbd2 kbd1 kbd0 figure 17-22. port g data register (ptg) address: $000e bit 7654321bit 0 read: 0 0 0 0 0 ddrg2 ddrg1 ddrg0 write: reset:00000000 figure 17-23. data dir ection regist er g (ddrg)
input/output (i/o) ports technical data mc68hc908ab32 ? rev. 1.1 334 input/output (i/o) ports freescale semiconductor ddrg[2:0] ? data direction register g bits these read/write bits control port g data direction. reset clears ddrg[2:0], configuring al l port g pins as inputs. 1 = corresponding port g pi n configured as output 0 = corresponding port g pin configured as input note: avoid glitches on port g pi ns by writing to the por t g data register before changing data direction regist er g bits from 0 to 1. figure 17-24 shows the port g i/o logic. figure 17-24. port g i/o circuit when ddrgx is a logic 1, reading address $000a reads the ptgx data latch. when ddrgx is a logic 0, reading address $000a reads the voltage level on the pin. the data la tch can always be written, regardless of the state of its data direction bit. table 17-6 summarizes the operat ion of the port g pins. table 17-8. port g pin functions ddrg bit ptg bit i/o pin mode accesses to ddrg accesses to ptg read/write read write 0x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddrg[2:0] pin ptg[2:0] (3) 3. writing affects data register, but does not affect the input. 1 x output ddrg[2:0] ptg[2:0] ptg[2:0] read ddrg ($000e) write ddrg ($000e) reset write ptg ($000a) read ptg ($000a) ptgx ddrgx ptgx internal data bus kbi
input/output (i/o) ports mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 335 17.10 port h port h is a 2-bit special-function port that shares all two of its pins with the keyboard interrupt (kbi) module. 17.10.1 port h data register (pth) the port h data register (pth) contains a data latch for each of the two port h pins. pth[1:0] ? port h data bits these read/write bits are software programmable. data direction of each port h pin is under the control of the corresponding bit in data direction register h. reset has no effect on port h data. kbd[4:3] ? the keyboard interrupt enable bits, kbie[4:3], in the keyboard interrupt enable register (kbier ), enable the port h pins as external interrupt pins. see section 19. keyboard interrupt module (kbi) . 17.10.2 data direction register h (ddrh) data direction register h determines whether eac h port h pin is an input or an output. writing l ogic 1 to a ddrh bit enabl es the output buffer for the corresponding port h pin; a logi c 0 disables the output buffer. address: $000b bit 7654321bit 0 read: 0 0 0 0 0 0 pth1 pth0 write: reset: unaffected by reset alternative function: kbd4 kbd3 figure 17-25. port h data register (pth)
input/output (i/o) ports technical data mc68hc908ab32 ? rev. 1.1 336 input/output (i/o) ports freescale semiconductor ddrh[1:0] ? data dire ction register h bits these read/write bits control port h data direction. reset clears ddrh[1:0], configuring all port h pins as inputs. 1 = corresponding port h pin configured as output 0 = corresponding port h pin configured as input note: avoid glitches on port h pins by writ ing to the port h dat a register before changing data direction register h bits from 0 to 1. figure 17-27 shows the port h i/o logic. figure 17-27. port h i/o circuit when ddrhx is a logic 1, reading address $000b reads the pthx data latch. when ddrhx is a logic 0, reading address $000b reads the voltage level on the pin. the data la tch can always be written, regardless of the state of its data direction bit. table 17-6 summarizes the operat ion of the port h pins. address: $000f bit 7654321bit 0 read: 0 0 0 0 0 0 ddrh1 ddrh0 write: reset:00000000 figure 17-26. data dir ection register h (ddrh) read ddrh ($000f) write ddrh ($000f) reset write pth ($000b) read pth ($000b) pthx ddrhx pthx internal data bus kbi
input/output (i/o) ports mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 337 table 17-9. port h pin functions ddrh bit pth bit i/o pin mode accesses to ddrh accesses to pth read/write read write 0x (1) input, hi-z (2) ddrh[1:0] pin pth[1:0] (3) 1 x output ddrh[1:0] pth[1:0] pth[1:0] notes : 1. x = don?t care. 2. hi-z = high impedance. 3. writing affects data register, but does not affect the input.
input/output (i/o) ports technical data mc68hc908ab32 ? rev. 1.1 338 input/output (i/o) ports freescale semiconductor
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor external interrupt (irq) 339 technical data ? mc68hc908ab32 section 18. external interrupt (irq) 18.1 contents 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .340 18.4.1 irq pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 18.5 irq status and control register (iscr) . . . . . . . . . . . . . . . . 343 18.6 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 344 18.2 introduction the irq (external interrupt) module pr ovides a maskable interrupt input. 18.3 features features of the irq modul e include the following: a dedicated external interrupt pin, i rq irq interrupt control bits hysteresis buffer programmable edge-only or edge and level interrupt sensitivity automatic interrupt acknowledge internal pullup resistor
external interrupt (irq) technical data mc68hc908ab32 ? rev. 1.1 340 external interrupt (irq) freescale semiconductor 18.4 functional description a logic 0 applied to the ex ternal interrupt pin ca n latch a cpu interrupt request. figure 18-1 shows the structure of the irq module. interrupt signals on the irq pin are latched into the irq latch. an interrupt latch remains set until on e of the following actions occurs: vector fetch ? a vector fetch au tomatically generates an interrupt acknowledge signal that clears the irq latch. software clear ? software can clea r the interrupt latch by writing to the acknowledge bit in the inte rrupt status and control register (iscr). writing a logi c 1 to the ack bit clears the irq latch. reset ? a reset automatically clears the interrupt latch. the external interrupt pin is fal ling-edge-triggered and is software- configurable to be either falli ng-edge or falling-edge and low-level- triggered. the mode bit in the iscr controls the tri ggering sensitivity of the irq pin. when the interrupt pin is edge-trigger ed only, the cpu interrupt request remains set until a vector fetch, software clear, or reset occurs. when the interrupt pin is both fallin g-edge and low-leve l-triggered, the cpu interrupt request remains set unt il both of the following occur: vector fetch or software clear return of the interr upt pin to logic 1 the vector fetch or software clear ma y occur before or af ter the interrupt pin returns to logic 1. as long as the pin is low, t he interrupt request remains pending. a reset will clear the la tch and the mode control bit, thereby clearing the interrup t even if the pin stays low. when set, the imask bi t in the iscr mask all external interrupt requests. a latched interrupt request is not pres ented to the interrupt priority logic unless t he imask bit is clear.
external interrupt (irq) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor external interrupt (irq) 341 note: the interrupt mask (i) in the conditi on code register (ccr) masks all interrupt requests, including external inte rrupt requests. (see 8.6 exception control .) figure 18-1. irq module block diagram ack imask dq ck clr irq high interrupt to mode select logic irq ff request v dd mode voltage detect synchro- nizer irqf to cpu for bil/bih instructions vector fetch decoder internal address bus reset v dd i nternal pullup device irq addr.register name bit 7654321bit 0 $001a irq status and control register (iscr) read: 0000irqf0 imask mode write: ack reset:00000000 = unimplemented figure 18-2. irq i/o register summary
external interrupt (irq) technical data mc68hc908ab32 ? rev. 1.1 342 external interrupt (irq) freescale semiconductor 18.4.1 irq pin a logic 0 on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear , or reset clears the irq latch. if the mode bit is set, the irq pin is both falling- edge-sensitive and low- level-sensitive. with mode set, both of the following actions must occur to clear irq: vector fetch or software clear ? a vector fetc h generates an interrupt acknowledge signal to cl ear the latch. software may generate the interrupt acknowledge si gnal by writing a logic 1 to the ack bit in the inte rrupt status and contro l register (iscr). the ack bit is useful in applic ations that poll the irq pin and require software to clear the irq latch. writing to the ac k bit prior to leaving an interrupt service rout ine can also prevent spurious interrupts due to noise. setting ack does not af fect subsequent transitions on the irq pin. a falling edge that occurs after writing to the ack bi t latches another interrupt request. if t he irq mask bit, imask, is clear, the cpu loads the progr am counter with the vector address at locations $fffa and $fffb. return of the irq pin to logic 1 ? as long as the irq pin is at logic 0, irq remains active. the vector fetch or software cl ear and the return of the irq pin to logic 1 may occur in any order. the inte rrupt request remains pending as long as the irq pin is at logic 0. a reset will clear the latch and the mode control bit, thereby cl earing the interrupt even if the pin stays low. if the mode bit is clear, the irq pin is falling-edge- sensitive only. with mode clear, a vector fetc h or software clear im mediately clears the irq latch. the irqf bit in the i scr register can be us ed to check for pending interrupts. the irqf bit is not affect ed by the imask bit, which makes it useful in applications wh ere polling is preferred. use the bih or bil in struction to read the logic level on the irq pin. note: when using the level-sensit ive interrupt trigger, av oid false interrupts by masking interrupt requests in the interrupt routine.
external interrupt (irq) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor external interrupt (irq) 343 18.5 irq status and co ntrol register (iscr) the irq status and control register (iscr) controls and monitors operation of the irq m odule. the iscr has the following functions: shows the state of the irq flag clears the irq latch masks irq interrupt request controls triggering se nsitivity of the irq interrupt pin irqf ? irq flag this read-only status bi t is high when the irq interrupt is pending. 1 = irq interrupt pending 0 = irq interr upt not pending ack ? irq interrupt request acknowledge bit writing a logic 1 to this write-only bit clears the irq latch. ack always reads as logic 0. reset clears ack. imask ? irq interrupt mask bit writing a logic 1 to this read/write bit disables irq interrupt requests. reset clears imask. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode ? irq edge/lev el select bit this read/write bit cont rols the triggering se nsitivity of the irq pin. reset clears mode. 1 = irq interrupt requests on falling edges and low levels 0 = irq interrupt reques ts on falling edges only address: $001a bit 7654321bit 0 read: 0000irqf0 imask mode write: ack reset:00000000 = unimplemented figure 18-3. irq status and control register (iscr)
external interrupt (irq) technical data mc68hc908ab32 ? rev. 1.1 344 external interrupt (irq) freescale semiconductor 18.6 irq module during break interrupts the system integration module (sim) co ntrols whether the irq latch can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear the latches during the break state. (see section 8. system in tegration module (sim) .) to allow software to clear the irq la tch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared dur ing the break state, it remains cleared when the m cu exits the break state. to protect the latches during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), writi ng to the ack bit in the irq status and control regi ster during the break state has no effect on the irq latch.
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor keyboard interrupt module (kbi) 345 technical data ? mc68hc908ab32 section 19. keyboard interrupt module (kbi) 19.1 contents 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 19.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 19.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 19.5.1 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 19.5.2 keyboard status and control register. . . . . . . . . . . . . . . . 349 19.5.3 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 351 19.6 wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 19.7 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 19.8 keyboard module during break interrupts . . . . . . . . . . . . . . . 352 19.2 introduction the keyboard interrupt module (kbi ) provides five independently maskable external interrupts whic h are accessible via ptg0?ptg2 and pth0?pth1 pins.
keyboard interrupt module (kbi) technical data mc68hc908ab32 ? rev. 1.1 346 keyboard interrupt module (kbi) freescale semiconductor 19.3 features features of the keyboard interr upt module inclu de the following: five keyboard interrupt pins with pullup devices separate keyboard in terrupt enable bits and one keyboard interrupt mask built-in pull-up device if input pin is configur ed as input port bit programmable edge-only or edge- and level- interrupt sensitivity exit from low-power modes 19.4 i/o pins the five keyboard interrupt pins ar e shared with standar d port i/o pins. the full name of the kbi pins are listed in table 19-1 . the generic pin name appear in the te xt that follows. addr.register name bit 7654321bit 0 $001b keyboard status and control register (kbscr) read:0000 keyf 0 imaskk modek write: ackk reset:00000000 $0021 keyboard interrupt enable register (kbier) read: 0 0 0 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 19-1. kbi i/o register summary table 19-1. pin name conventions kbi generic pin name full mcu pin name pin selected for kbi function by kbiex bit in kbier kbd0 ptg0/kbd0 kbie0 kbd1 ptg1/kbd1 kbie1 kbd2 ptg2/kbd2 kbie2 kbd3 pth0/kbd3 kbie3 kbd4 pth1/kbd4 kbie4
keyboard interrupt module (kbi) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor keyboard interrupt module (kbi) 347 19.5 functional description figure 19-2. keyboard in terrupt block diagram writing to the kbie4?kbie0 bits in the keyboard interrupt enable register independently enables or disables th e corresponding port pin as a keyboard interrupt pin. en abling a keyboard interrupt pin also enables its internal pull-up device. a logi c 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. a keyboard interrupt is latched w hen one or more keyboard pins goes low after all were high. the modek bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. if the keyboard interrupt is e dge-sensitive only, a falling edge on a keyboard pin does not latch an in terrupt reques t if another keyboard pin is already low. to pr event losing an interrupt request on one pin because another pin is still low, software can disable the latter pin wh ile it is low. if the keyboard interrupt is falli ng edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. if the modek bit is set, the keyboard interrupt pins ar e both falling edge- and low level-sensitive, and both of t he following actions must occur to clear a keyboard interrupt request: kbie0 kbie4 . . . dq ck clr v dd modek imaskk keyboard interrupt ff vector fetch decoder ackk internal bus reset kbd4 kbd0 synchronizer keyf keyboard interrupt request to pullup enable to pullup enable
keyboard interrupt module (kbi) technical data mc68hc908ab32 ? rev. 1.1 348 keyboard interrupt module (kbi) freescale semiconductor vector fetch or software clear ? a vector fetc h generates an interrupt acknowledge signal to clear the interrupt request. software may generate the inte rrupt acknowle dge signal by writing a logic 1 to t he ackk bit in the keyboa rd status and control register kbscr. the ackk bit is useful in app lications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine can al so prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that occurs after writing to the ackk bi t latches another inte rrupt request. if the keyboard interrupt mask bit, imask k, is clear, the cpu loads the program counter with the vector address at locations $ffd2 and $ffd3. return of all enabled keyboard interr upt pins to logic 1 ? as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. if the modek bit is clear, the key board interrupt pin is falling-edge- sensitive only. with mo dek clear, a vector fetc h or software clear immediately clears the ke yboard interrupt request. reset clears the keyboard interrupt request and the modek bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. the keyboard flag bit (keyf) in the ke yboard status and control register can be used to see if a pending inte rrupt exists. the keyf bit is not affected by the keyboard interrupt mask bit (imaskk) which makes it useful in applications wh ere polling is preferred. to determine the logic level on a key board interrupt pin, disable the pull- up device, use the data direction regist er to configure t he pin as an input and then read the data register. note: setting a keyboard interrupt enable bi t (kbiex) forces the corresponding keyboard interrupt pin to be an inpu t, overriding t he data direction register. however, the dat a direction register bi t must be a logic 0 for software to read the pin.
keyboard interrupt module (kbi) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor keyboard interrupt module (kbi) 349 19.5.1 keyboard initialization when a keyboard interrupt pin is enabl ed, it takes time for the internal pull-up to reach a logic 1. therefor e a false interrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by se tting the imaskk bit in the keyboard status and control register. 2. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 3. write to the ackk bit in the keyboard status and control register to clear any false interrupts. 4. clear the imaskk bit. an interrupt signal on an edg e-triggered pin can be acknowledged immediately after enabling the pin. an interrupt si gnal on an edge- and level-triggered interrupt pin must be acknowledged afte r a delay that depends on the external load. another way to avoi d a false interrupt: 1. configure the keyboard pins as outputs by setting the appropriate ddr bits in the data direction register. 2. write logic 1s to the appropria te port data register bits. 3. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 19.5.2 keyboard status and control register flags keyboard interrupt requests. acknowledges keyboard interrupt requests. masks keyboard interrupt requests. controls keyboard interrupt triggering sensitivity.
keyboard interrupt module (kbi) technical data mc68hc908ab32 ? rev. 1.1 350 keyboard interrupt module (kbi) freescale semiconductor bits 7?4 ? not used these read-only bits alwa ys read as logic 0s. keyf ? keyboard flag bit this read-only bit is set when a ke yboard interrupt is pending. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending ackk ? keyboard acknowledge bit writing a logic 1 to th is write-only bit clears the keyboard interrupt request. ackk always reads as logic 0. rese t clears ackk. imaskk? keyboard interrupt mask bit writing a logic 1 to th is read/write bit prev ents the output of the keyboard interrupt mask from gene rating interrupt requests. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modek ? keyboard tri ggering sensitivity bit this read/write bit controls the tri ggering sensitivity of the keyboard interrupt pins. reset clears modek. 1 = keyboard interrupt reques ts on falling edges and low levels 0 = keyboard interrupt requests on falling edges only address: $001b bit 7654321bit 0 read: 0000 keyf 0 imaskk modek write: ackk reset:00000000 = unimplemented figure 19-3. keyboard status and control regi ster (kbscr)
keyboard interrupt module (kbi) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor keyboard interrupt module (kbi) 351 19.5.3 keyboard interrupt enable register the keyboard interrupt enable regist er enables or disables the corresponding port pin to operate as a keyboard interrupt pin. kbie4?kbie0 ? keyboard interrupt enable bits each of these read/write bits enables the corres ponding keyboard interrupt pin to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = kbdx pin enabled as ke yboard interrupt pin 0 = kbdx pin not enabled as keyboard interrupt pin 19.6 wait mode the keyboard modules remain active in wait mode. clearing the imaskk bit in the keyboar d status and control r egister enables keyboard interrupt requests to brin g the mcu out of wait mode. 19.7 stop mode the keyboard module remains active in stop mode. clearing the imaskk bit in the keyboar d status and control r egister enables keyboard interrupt requests to bring the mcu out of stop mode. address: $0021 bit 7654321bit 0 read: 0 0 0 kbie4 kbie3 kbie2 kbie1 kbie0 write: port pin: pth1/ kbd4 pth0/ kbd3 ptg2/ kbd2 ptg1/ kbd1 ptg0 /kbd0 reset:00000000 figure 19-4. keyboard interr upt enable register (kbier)
keyboard interrupt module (kbi) technical data mc68hc908ab32 ? rev. 1.1 352 keyboard interrupt module (kbi) freescale semiconductor 19.8 keyboard module during break interrupts the system integration module (sim) controls whether the keyboard interrupt latch can be cleared during t he break state. the bcfe bit in the break flag control register (bfcr) enabl es software to clear status bits during the break state. to allow software to clear the key board interrupt la tch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared w hen the mcu exits the break state. to protect the latch during the break st ate, write a logi c 0 to the bcfe bit. with bcfe at logi c 0 (its default state), writing to the keyboard acknowledge bit (ackk) in the keyboard status and control register during the break state has no effect.
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor computer operating properly (cop) 353 technical data ? mc68hc908ab32 section 20. computer operating properly (cop) 20.1 contents 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 20.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354 20.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 20.4.1 cgmxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355 20.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 20.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355 20.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 20.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 20.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 20.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 20.4.8 coprs (cop rate sele ct) . . . . . . . . . . . . . . . . . . . . . . . . 356 20.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 20.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 20.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 20.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 20.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 20.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 20.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 358 20.2 introduction the computer operating properly (cop ) module contains a free-running counter that generates a reset if allowed to overflow. the cop module helps software recover from runa way code. prevent a cop reset by clearing the cop counter periodically. the cop module can be disabled through the copd bit in confi guration register 1 (config1).
computer operating properly (cop) technical data mc68hc908ab32 ? rev. 1.1 354 computer operating properly (cop) freescale semiconductor 20.3 functional description figure 20-1 shows the structure of the cop module. figure 20-1. cop block diagram the cop counter is a free-running 6- bit counter preceded by a 12-bit prescaler counter. if not cleared by software, the cop counter overflows and generates an asynchr onous reset after 2 18 ?2 4 or 2 13 ?2 4 cgmxclk cycles, depending on the state of the co p rate select bit, coprs, in configuration register 1. with a 2 18 ?2 4 cgmxclk cycle overflow option, a 4. 9152mhz crystal gives a cop timeout period of 53.3ms. writing any value to locati on $ffff before an overflow occurs prevents a cop reset by clearing the cop counter and stages 12 through 5 of the prescaler. note: service the cop immediately after re set and before entering or after exiting stop mode to guarantee the ma ximum time before the first cop counter overflow. copctl write cgmxclk reset vector fetch reset circuit reset status register internal reset sources 12-bit cop prescaler clear all stages 6-bit cop counter cop disable reset copctl write clear cop module copen (from sim) cop counter cop clock cop timeout stop instruction (copd from config1) cop rate sel (coprs from config1) clear stages 5?12
computer operating properly (cop) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor computer operating properly (cop) 355 a cop reset pulls the rst pin low for 32 cgm xclk cycles and sets the cop bit in the sim reset status register (srsr). in monitor mode, the cop is disabled if the rst pin or the irq is held at v tst during the break state, v tst on the rst pin disables the cop. note: place cop clearing instructions in the main program and not in an interrupt subroutine. su ch an interrupt subrout ine could keep the cop from generating a reset even while the main pr ogram is not working properly. 20.4 i/o signals the following paragraphs descri be the signals shown in figure 20-1 . 20.4.1 cgmxclk cgmxclk is the crystal oscillator output si gnal. cgmxclk frequency is equal to the crystal frequency. 20.4.2 stop instruction the stop instruction cl ears the cop prescaler. 20.4.3 copctl write writing any value to the cop control register (copctl) (see 20.5 cop control register ) clears the cop counter a nd clears bits 12 through 5 of the prescaler. reading the cop cont rol register retu rns the low byte of the reset vector. 20.4.4 power-on reset the power-on reset (por) circuit clears the cop prescaler 4096 cgmxclk cycles after power-up.
computer operating properly (cop) technical data mc68hc908ab32 ? rev. 1.1 356 computer operating properly (cop) freescale semiconductor 20.4.5 internal reset an internal reset clears the co p prescaler and the cop counter. 20.4.6 reset vector fetch a reset vector fetch occurs when the vector addres s appears on the data bus. a reset vector fetch clears the cop prescaler. 20.4.7 copd (cop disable) the copd signal reflec ts the state of the cop di sable bit (copd) in the configuration re gister 1. (see figure 20-2 .) 20.4.8 coprs (cop rate select) the coprs signal reflects the state of the cop ra te select bit (coprs) in the configurati on register 1. (see figure 20-2 .) coprs ? cop rate select bit coprs selects the cop timeout period. rese t clears coprs. 1 = cop timeout period is 2 18 ? 2 4 cgmxclk cycles 0 = cop timeout period is 2 13 ? 2 4 cgmxclk cycles copd ? cop disable bit copd disables the cop module. 1 = cop module disabled 0 = cop module enabled address: $001f bit 7654321bit 0 read: lvistop r lvirstd lvipwrd ssrec coprs stop copd write: reset:00000000 r=reserved figure 20-2. configurati on register 1 (config1)
computer operating properly (cop) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor computer operating properly (cop) 357 20.5 cop control register the cop control register is locat ed at address $ffff and overlaps the reset vector. writing any value to $ffff clears t he cop counter and starts a new timeout per iod. reading location $ffff returns the low byte of the reset vector. 20.6 interrupts the cop does not generate cpu interrupt requests. 20.7 monitor mode when monitor mode is entered with v tst on the irq pin, the cop is disabled as long as v tst remains on the irq pin or the rst pin. when monitor mode is enter ed by having blank rese t vectors and not having v tst on the irq pin, the cop is automatically di sabled until a por occurs. 20.8 low-power modes the wait and stop in structions put the mcu in low power- consumption standby modes. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 20-3. cop cont rol register (copctl)
computer operating properly (cop) technical data mc68hc908ab32 ? rev. 1.1 358 computer operating properly (cop) freescale semiconductor 20.8.1 wait mode the cop remains active during wait mode. to prevent a cop reset during wait mode, periodi cally clear the cop counter in a cpu interrupt routine. 20.8.2 stop mode stop mode turns off the cgmxclk i nput to the cop a nd clears the cop prescaler. service the co p immediately before ent ering or after exiting stop mode to ensure a full cop timeout period a fter entering or exiting stop mode. to prevent inadvertently turning off t he cop with a stop instruction, a configuration option is av ailable that disables the stop instruction. when the stop bit in the config uration register has the stop instruction is disabled, execution of a stop in struction results in an illegal opcode reset. 20.9 cop module during break mode the cop is disabled during a break interrupt when v tst is present on the rst pin.
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor low-voltage inhibit (lvi) 359 technical data ? mc68hc908ab32 section 21. low-voltage inhibit (lvi) 21.1 contents 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 21.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 21.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .360 21.4.1 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 21.4.2 forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . .361 21.4.3 false reset protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 21.5 lvi status register (lvisr) . . . . . . . . . . . . . . . . . . . . . . . . . . 362 21.6 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362 21.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 21.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363 21.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363 21.2 introduction this section describes the low-volt age inhibit module, which monitors the voltage on the v dd pin and can force a reset when the v dd voltage falls to the lv i trip voltage. 21.3 features features of the lvi modu le include the following: programmable lvi reset programmable lvi module power programmable st op mode operation
low-voltage inhibit (lvi) technical data mc68hc908ab32 ? rev. 1.1 360 low-voltage inhibit (lvi) freescale semiconductor 21.4 functional description figure 21-1 shows the structur e of the lvi module. the lvi is enabled out of reset. the lvi module cont ains a bandgap reference circuit and comparator. the lvi power bit, lvip wrd, enables the lvi to monitor v dd voltage. the lvi rese t bit, lvirstd, enables the lvi module to generate a reset when v dd falls below a voltage, lvi tripf , and remains at or below that level for 9 or more consecutiv e cpu cycles. setting the lvi enable in stop mode bit, lvistop, enables the lvi to operate in stop mode. lvistop, lvipwrd, and lvirstd are in the c onfiguration register 1 (config1). see section 6. configurat ion register (config) for details of the lvi?s conf iguration bits. once an lv i reset occurs, the mcu remains in reset until v dd rises above a voltage, lvi tripr , which causes the mcu to exit reset. see 8.4.2.5 low-voltage inhibit (lvi) reset for details of the interactio n between the sim and the lv i. the output of the comparator controls the state of t he lviout flag in the lvi status register (lvisr). an lvi reset also drives the rst pin low to provide low-voltage protection to external peripheral devices. note: where lvi trip falling voltage lvi tripf = v lvii and lvi trip rising voltage lvi tripr = v lvii + h lvi (see section 23. electri cal specifications .) figure 21-1. lvi module block diagram low v dd detector lv i p w r d stop instruction lv i s to p lvi reset lv i o u t v dd > lvi trip = 0 v dd lvi trip = 1 from config1 from config1 v dd from config1 lv i r s t d to lvisr
low-voltage inhibit (lvi) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor low-voltage inhibit (lvi) 361 21.4.1 polled lvi operation in applications that can operate at v dd levels below the lvi tripf level, software can monitor v dd by polling the lviout bi t. in configuration register 1, the lvipwrd bi t must be at logic 0 to enable the lvi module, and the lvirstd bi t must be at logic 1 to disable lvi resets. 21.4.2 forced reset operation in applications that require v dd to remain above the lvi tripf level, enabling lvi resets allows the lvi module to reset the mcu when v dd falls below the lvi tripf level and remains at or below that level for 9 or more consecutive cpu cycles. in conf iguration register 1, the lvipwrd and lvirstd bits must be at logic 0 to enable the lv i module and to enable lvi resets. 21.4.3 false reset protection the v dd pin level is digitally filtered to reduce false resets due to power supply noise. in order for the lv i module to reset the mcu, v dd must remain at or below the lvi tripf level for 9 or mo re consecutive cpu cycles. v dd must be above lvi tripr for only one cpu cycle to bring the mcu out of reset. address: $fe0f bit 7654321bit 0 read: lviout 0 0 0 0 0 0 0 write: reset:00000000 = unimplemented figure 21-2. lvi i/o register summary
low-voltage inhibit (lvi) technical data mc68hc908ab32 ? rev. 1.1 362 low-voltage inhibit (lvi) freescale semiconductor 21.5 lvi status register (lvisr) the lvi status register flags v dd voltages below the lvi tripf level . lviout ? lvi output bit this read-only flag bec omes set when v dd falls below the lvi tripf voltage for 32 to 40 cgmxclk cycles. (see table 21-1 .) reset clears the lviout bit. 21.6 lvi interrupts the lvi module does not gener ate interrupt requests. address: $fe0f bit 7654321bit 0 read: lviout 0 0 0 0 0 0 0 write: reset:00000000 = unimplemented figure 21-3. lvi stat us register (lvisr) table 21-1. lviout bit indication v dd lviout at level: for number of cgmxclk cycles: v dd > lvi tripr any 0 v dd < lv i tripf < 32 cgmxclk cycles 0 v dd < lv i tripf 32 to 40 cgmxclk cycles 0 or 1 v dd < lv i tripf > 40 cgmxclk cycles 1 lv i tripf < v dd < lv i tripr any previous value
low-voltage inhibit (lvi) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor low-voltage inhibit (lvi) 363 21.7 low-power modes the stop and wait instructions put the mcu in low power- consumption standby modes. 21.7.1 wait mode if enabled, the lvi module remains acti ve in wait mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of wait mode. 21.7.2 stop mode if enabled in stop mode (l vistop set), the lvi module remains active in stop mode. if enabled to gener ate resets, the lvi module can generate a reset and bring t he mcu out of stop mode.
low-voltage inhibit (lvi) technical data mc68hc908ab32 ? rev. 1.1 364 low-voltage inhibit (lvi) freescale semiconductor
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor break module (brk) 365 technical data ? mc68hc908ab32 section 22. break module (brk) 22.1 contents 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 22.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 22.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366 22.4.1 flag protection during break interr upts . . . . . . . . . . . . . . . 368 22.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . .368 22.4.3 pit, tima, and timb during break interrupts . . . . . . . . . . 368 22.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 368 22.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 22.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368 22.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369 22.6 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 22.6.1 break status and control register. . . . . . . . . . . . . . . . . . . 369 22.6.2 break address register s . . . . . . . . . . . . . . . . . . . . . . . . . . 370 22.6.3 sim break status regi ster . . . . . . . . . . . . . . . . . . . . . . . . . 370 22.6.4 sim break flag control register . . . . . . . . . . . . . . . . . . . . 372 22.2 introduction this section describes the break module (brk). the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program.
break module (brk) technical data mc68hc908ab32 ? rev. 1.1 366 break module (brk) fre escale semiconductor 22.3 features features of the br eak module include: accessible input/output (i/o) regi sters during the break interrupt cpu-generated break interrupts software-generated break interrupts cop disabling during break interrupts 22.4 functional description when the internal address bus matches the value written in the break address registers, the br eak module issues a breakpoint signal to the cpu. the cpu then loads the instruct ion register with a software interrupt instruction (swi) afte r completion of the current cpu instruction. the progr am counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: a cpu-generated address (the addr ess in the program counter) matches the contents of th e break address registers. software writes a logic 1 to the brka bit in the break status and control register. when a cpu-generated addre ss matches the contents of the break address registers, th e break interrupt begins af ter the cpu completes its current instruction. a return-from-inter rupt instruction (r ti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 22-1 shows the structure of the break module.
break module (brk) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor break module (brk) 367 figure 22-1. break module block diagram iab15?iab8 iab7?iab0 8-bit comparator 8-bit comparator control break address register low break address register high iab15?iab0 break addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset:00000000 $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe0c break address register high (brkh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0d break address register low (brkl) read: bit 7654321bit 0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 note: writing a logic 0 clears sbsw. = unimplemented r = reserved figure 22-2. break module i/o register summary
break module (brk) technical data mc68hc908ab32 ? rev. 1.1 368 break module (brk) fre escale semiconductor 22.4.1 flag protection during break interrupts the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bi ts during the break state. 22.4.2 cpu during break interrupts the cpu starts a br eak interrupt by: loading the instruction regist er with the swi instruction loading the program counter with $fffc and $fffd ($fefc and $fefd in monitor mode) the break interrupt begins after completion of t he cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. 22.4.3 pit, tima, and timb during break interrupts a break interrupt stops all timer counters. 22.4.4 cop during break interrupts the cop is disabled during a break interrupt when v tst is present on the rst pin. 22.5 low-power modes the wait and stop in structions put the mcu in low power- consumption standby modes. 22.5.1 wait mode if enabled, the break module is active in wait mode. in the break routine, the user can subtract one from the re turn address on the stack if sbsw is set (see section 8. system in tegration module (sim) ). clear the sbsw bit by writi ng logic 0 to it.
break module (brk) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor break module (brk) 369 22.5.2 stop mode a break interrupt causes exit from stop mode and sets the sbsw bit in the break status register. 22.6 break module registers these registers control and monitor operation of the break module: break status and cont rol register (brkscr) break address regi ster high (brkh) break address regi ster low (brkl) sim break status register (sbsr) sim break flag control register (sbfcr) 22.6.1 break status and control register the break status and control register (brkscr) contai ns break module enable and status bits. brke ? break enable bit this read/write bit enabl es breaks on break address register matches. clear brke by writing a logic 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16 -bit address match 0 = breaks disabled on 16-bit address match address: $fe0e bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 22-3. break status an d control register (brkscr)
break module (brk) technical data mc68hc908ab32 ? rev. 1.1 370 break module (brk) fre escale semiconductor brka ? break active bit this read/write status and control bit is se t when a break address match occurs. writing a logic 1 to brka generates a break interrupt. clear brka by writing a logic 0 to it before exiting the break routine. reset clears the brka bit. 1 = (when read) br eak address match 0 = (when read) no break address match 22.6.2 break address registers the break address register s (brkh and brkl) contai n the high and low bytes of the desired brea kpoint address. reset clears the break address registers. 22.6.3 sim break status register the sim break status register (sbsr) contains a flag to indicate that a break caused an exit from wait mode. the flag is useful in applications requiring a return to wait mode a fter exiting from a break interrupt. address: $fe0c bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 figure 22-4. break addres s register high (brkh) address: $fe0d bit 7654321bit 0 read: bit 7654321bit 0 write: reset:00000000 figure 22-5. break addr ess register low (brkl)
break module (brk) mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor break module (brk) 371 sbsw ? sim break stop/wait bit this status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. clear sbsw by writing a logic 0 to it. re set clears sbsw. 1 = stop mode or wa it mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt sbsw can be read within the break interrupt routine. the user can modify the return address on the st ack by subtractin g one from it. the following code is an example. address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note reset:00000000 note: writing a logic 0 clears sbsw. r= reserved figure 22-6. sim break stat us register (sbsr) ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ;if returnlo is not zero, bne dolo ;then just decrement low byte. dec hibyte,sp ;else deal with high byte, too. dolo dec lobyte,sp ;point to wait/stop opcode. return pulh rti ;restore h register.
break module (brk) technical data mc68hc908ab32 ? rev. 1.1 372 break module (brk) fre escale semiconductor 22.6.4 sim break flag control register the sim break flag control register (s bfcr) contains a bit that enables software to clear status bits wh ile the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to cl ear status bits during the break state, t he bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 22-7. sim break flag c ontrol register (sbfcr)
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor electrical specifications 373 technical data ? mc68hc908ab32 section 23. electrical specifications 23.1 contents 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 23.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 374 23.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 375 23.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 23.6 5.0-v dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . 376 23.7 eeprom and memory characteristics . . . . . . . . . . . . . . . . . 377 23.8 5.0-v control timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 23.9 timer interface module characteristics . . . . . . . . . . . . . . . . . 378 23.10 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 23.11 spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 23.12 clock generation module characteristics . . . . . . . . . . . . . . . 383 23.12.1 cgm operating condition s . . . . . . . . . . . . . . . . . . . . . . . . 383 23.12.2 cgm component informat ion . . . . . . . . . . . . . . . . . . . . . . 383 23.12.3 cgm acquisition/lock time inform ation . . . . . . . . . . . . . . 384 23.13 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . 385 23.2 introduction this section contains electrical and timing specifications.
electrical specifications technical data mc68hc908ab32 ? rev. 1.1 374 electrical specifications freescale semiconductor 23.3 absolute maximum ratings maximum ratings are t he extreme limits to which the mcu can be exposed without perman ently damaging it. note: this device is not guar anteed to operate properly at the maximum ratings. refer to 23.6 5.0-v dc electri cal characteristics for guaranteed operating conditions . note: this device contains circ uitry to protect the i nputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applic ation of any voltage higher than maximum-rated voltages to this hi gh-impedance circui t. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of oper ation is enhanced if unused inputs are co nnected to an appropriate logic voltage level (for example, either v ss or v dd ). characteristic (1) notes : 1. voltages referenced to v ss symbol value unit supply voltage v dd ?0.3 to + 6.0 v input voltage v in v ss ? 0.3 to v dd + 0.3 v maximum current per pin excluding v dd , v ss , and ptd0?ptd7 i 15 ma maximum current for pins ptd0?ptd7 i ptd0?ptd7 25 ma maximum current into v dd i mvdd 100 ma maximum current out of v ss i mvss 100 ma storage temperature t stg ?55 to +150 c
electrical specifications mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor electrical specifications 375 23.4 functional operating range 23.5 thermal characteristics characteristic symbol value unit operating temperature range t a ?40 to +85 ?40 to +125 c operating voltage range v dd 5.0 10% 5.0 10% v characteristic symbol value unit thermal resistance qfp (64-pin) ja 70 c/w i/o pin power dissipation p i/o user-determined w power dissipation (1) notes : 1. power dissipation is a function of temperature. p d p d = (i dd v dd ) + p i/o = k/(t j + 273 c) w constant (2) 2. k is a constant unique to the device. k can be determined for a known t a and measured p d . with this value of k, p d and t j can be determined for any value of t a . k p d (t a + 273 c ) + p d 2 ja w / c average junction temperature t j t a + (p d ja ) c
electrical specifications technical data mc68hc908ab32 ? rev. 1.1 376 electrical specifications freescale semiconductor 23.6 5.0-v dc electr ical characteristics characteristic (1) symbol min typ (2) max unit output high voltage (i load = ?2.0 ma) all i/o pins (i load = ?10.0 ma) all i/o pins (i load = ?10.0 ma) pins ptd0?ptd7 only maximum combined i oh for port c, port e, port f, port g, port h maximum combined i oh for port d, port a, port b maximum total i oh for all port pins v oh v oh v oh i oh1 i oh2 i oht v dd ? 0.8 v dd ? 1.5 v dd ? 0.8 ? ? ? ? ? ? ? ? ? ? ? ? 50 50 100 v v v ma ma ma output low voltage (i load = 1.6 ma) all i/o pins (i load = 10 ma) all i/o pins (i load = 15 ma) pins ptd0?ptd7 only maximum combined i ol for port c, port e, port f, port g, port h maximum combined i ol for port d, port a, port b maximum total i ol for all port pins v ol v ol v ol i ol1 i ol2 i olt ? ? ? ? ? ? ? ? ? ? ? ? 0.4 1.5 1.0 50 50 100 v v v ma ma ma input high voltage all ports, irq , rst , osc1 v ih 0.7 v dd ? v dd v input low voltage all ports, irq , rst , osc1 v il v ss ? 0.3 v dd v v dd supply current run (3) wait (4) stop (5) lvi enabled, t a = 25 c lvi disabled, t a = 25 c lvi enabled, t a = ?40 c to 125 c lvi disabled, t a = ?40 c to 125 c i dd ? ? ? ? ? ? ? ? 300 20 400 50 30 12 400 50 500 100 ma ma a a a a i/o ports hi-z leakage current (6) i il ?1 10 a input current i in ??1 a pullup resistors (as input only) r pu 20 33 50 k ? capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf monitor mode entry voltage v tst v dd + 2.5 ?8v low-voltage inhibit, trip falling voltage ? target v lv i i ?4.11 ? v
electrical specifications mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor electrical specifications 377 23.7 eeprom and memory characteristics low-voltage inhibit reset/recover hysteresis ? target h lv i 100 150 ? mv por rearm voltage (7) v por 0?200mv por reset voltage (8) v porrst 0?800mv por rise time ramp rate (9) r por 0.02 ? ? v/ms notes : 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source (f bus = 8.4 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configur ed as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f bus = 8.4 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects wait i dd . measured with pll and lvi enabled. 5. stop i dd is measured with osc1 = v ss . 6. pullups are disabled. port b leakage is specified in 23.10 adc characteristics . 7. maximum is highest vo ltage that por is guaranteed. 8. maximum is highest vo ltage that por is possible. 9. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. characteristic symbol min max unit ram data retention voltage v rdr 0.7 ? v eeprom programming time per byte t eepgm 10 ? ms eeprom erasing time per byte t ebyte 10 ? ms eeprom erasing time per block t eblock 10 ? ms eeprom erasing time per bulk t ebulk 10 ? ms eeprom programming voltage discharge period t eefpv 100 ? s number of programming operations to the same eeprom byte before erase (1) notes : 1. programming a byte more times than the specified maximum may affect the data integrity of that byte. the byte must be erased before it can be programmed again. ??8? eeprom write/erase cycles at 10ms write time (85 c) ? 10,000 ? cycles eeprom data retention after 10 ,000 write/erase cycles ? 10 ? years characteristic (1) symbol min typ (2) max unit
electrical specifications technical data mc68hc908ab32 ? rev. 1.1 378 electrical specifications freescale semiconductor 23.8 5.0-v control timing 23.9 timer interface module characteristics characteristic (1) notes : 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted symbol min max unit frequency of operation crystal option (2) external clock option (3) 2. see 23.12 clock generation module characteristics for more information. 3. no more than 10% duty cycle deviation from 50% f osc 1 dc (4) 4. some modules may require a minimum fr equency greater than dc for proper operation. see appropriate table for this information. 8.4 33.6 mhz mhz internal operating frequency f bus note (5) 5. some modules may require a minimum fr equency greater than dc for proper operation. see appropriate table for this information. 8.4 mhz reset input pulse width low (6) 6. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. t irl 1.5 ? t cyc irq interrupt pulse width low (7) (edge-triggered) 7. minimum pulse width is for guaranteed interrupt. it is possible for a smaller pulse width to be recognized. t ilih 1.5 ? t cyc irq interrupt pulse period t ilil note (8) 8. minimum pulse width is for guaranteed interrupt. it is possible for a smaller pulse width to be recognized. the minimum period, t ilil or t tltl , should not be less than the number of cycles it takes to execute the in terrupt service routine plus tbd t cyc . ? t cyc 16-bit timer input capture pulse width input capture period t th, t tl t tltl 2 note (9) 9. the minimum period, t ilil or t tltl , should not be less than the number of cycles it takes to execute the interrupt service routine plus tbd t cyc . ? ? t cyc t cyc characteristic symbol min max unit input capture pulse width t tih , t til 125 ? ns input clock pulse width t tch , t tcl (1/f bus )+5 ?ns
electrical specifications mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor electrical specifications 379 23.10 adc characteristics characteristic (1) symbol min max unit comments supply voltage v ddad 4.5 (v dd min) 5.5 (v dd max) v v ddaref should be tied to the same potential as v dd via separate traces. input voltages v adin v refh 0 1.5 v ddaref v ddaref v v adin v refh resolution b ad 88bits absolute accuracy (v refl = 0 v, v refh = v ddad = 5 v 10%) a ad 1/2 1 lsb includes quantization adc internal clock f adic 0.5 1.048 mhz t aic = 1/f adic , tested only at 1 mhz conversion range r ad v refl v refh v v refl = v ssa power-up time t adpu 16 t aic cycles conversion time t adc 16 17 t aic cycles sample time (2) t ads 5? t aic cycles zero input reading (3) z adi 00 01 hex v in = v refl full-scale reading (3) f adi fe ff hex v in = v refh input capacitance c adi ? (20) 8 pf not tested input leakage (4) port b ?? 1 a notes : 1. v dd = 5.0 vdc 10%, v dda = v ddaref = 5.0 vdc 10%, v refh = 5.0 vdc 10%, v ss = 0 vdc, v refl = v ssa = 0 vdc 2. source impedances greater than 10 k ? adversely affect internal rc charging time during input sampling. 3. zero-input/full-scale reading requires sufficien t decoupling measures for accurate conversions. 4. the external system error caused by input leakage current is approximately equal to the product of r source and input current.
electrical specifications technical data mc68hc908ab32 ? rev. 1.1 380 electrical specifications freescale semiconductor 23.11 spi characteristics diagram number (1) notes : 1. numbers refer to dimensions in figure 23-1 and figure 23-2 . characteristic (2) 2. all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. symbol min max unit operating frequency master slave f bus(m) f bus(s) f bus /128 dc f bus /2 f bus mhz mhz 1 cycle time master slave t cyc(m) t cyc(s) 2 1 128 ? t cyc t cyc 2 enable lead time t lead(s) 15 ? ns 3 enable lag time t lag(s) 15 ? ns 4 clock (spsck) high time master slave t sckh(m) t sckh(s) 100 50 ? ? ns ns 5 clock (spsck) low time master slave t sckl(m) t sckl(s) 100 50 ? ? ns ns 6 data setup time (inputs) master slave t su(m) t su(s) 45 5 ? ? ns ns 7 data hold time (inputs) master slave t h(m) t h(s) 0 15 ? ? ns ns 8 access time, slave (3) cpha = 0 cpha = 1 3. time to data active from high-impedance state t a(cp0) t a(cp1) 0 0 40 20 ns ns 9 disable time, slave (4) 4. hold time to high-impedance state t dis(s) ?25ns 10 data valid time, after enable edge master slave (5) 5. with 100 pf on all spi pins t v(m) t v(s) ? ? 10 40 ns ns 11 data hold time, outputs, after enable edge master slave t ho(m) t ho(s) 0 5 ? ? ns ns
electrical specifications mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor electrical specifications 381 figure 23-1. spi master timing note note: this first clock edge is generated internally, but is not seen at the spsck pin. ss pin of master held high msb in ss input spsck output spsck output miso input mosi output note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 11 10 11 7 6 note note: this last clock edge is generated inte rnally, but is not seen at the spsck pin. ss pin of master held high msb in ss input spsck output spsck output miso input mosi output note 4 5 5 1 4 bits 6?1 lsb in master msb out bits 6?1 master lsb out 10 11 10 7 6 a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) cpol = 0 cpol = 1 cpol = 0 cpol = 1
electrical specifications technical data mc68hc908ab32 ? rev. 1.1 382 electrical specifications freescale semiconductor figure 23-2. spi slave timing note: not defined but normally msb of character just received slave ss input spsck input spsck input miso input mosi output 4 5 5 1 4 msb in bits 6?1 8 6 10 5 11 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out note: not defined but normally lsb of character previ ously transmitted slave ss input spsck input spsck input miso output mosi input 4 5 5 1 4 msb in bits 6?1 8 6 10 note slave lsb out 9 3 lsb in 2 7 bits 6?1 msb out 10 a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1) 11 11 cpol = 0 cpol = 1 cpol = 0 cpol = 1
electrical specifications mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor electrical specifications 383 23.12 clock generation module characteristics 23.12.1 cgm operating conditions 23.12.2 cgm component information characteristic symbol min typ max comments operating voltage v dd 4.5 v ? 5.5 v crystal reference frequency f rclk 1?8.4 module crystal reference frequency f xclk ? 4.9152 mhz ? same frequency as f rclk range nominal multiplier f nom ? 4.9152 mhz ? 4.5 to 5.5 v, v dd only vco center-of-range frequency (mhz) f vrs 4.9152 ? 32.0 4.5 to 5.5 v, v dd only vco operating frequency (mhz) f vclk 4.9152 ? 32.0 characteristic symbol min typ max unit crystal load capacitance c l ??? consult crystal manufacturer?s data crystal fixed capacitance c 1 ? 2 c l ? consult crystal manufacturer?s data crystal tuning capacitance c 2 ? 2 c l ? consult crystal manufacturer?s data feedback bias resistor r b ?22m ? ? series resistor r s ? 330k ? 1m ? not required filter capacitor multiply factor c fact ? 0.0154 ? f/s v filter capacitor c f ? c fact (v dda /f xclk) ? see 9.5.3 external filter capacitor pin (cgmxfc) . bypass capacitor c byp ?0.1 f? c byp must provide low ac impedance from f = f xclk /100 to 100 f vclk , so series resistance must be considered.
electrical specifications technical data mc68hc908ab32 ? rev. 1.1 384 electrical specifications freescale semiconductor 23.12.3 cgm acquisition/lock time information description (1) notes : 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. symbol min typ max notes manual mode time to stable t acq ? (8 v dda )/(f xclk k acq) ? if c f chosen correctly manual stable to lock time t al ? (4 v dda )/(f xclk k trk ) ? if c f chosen correctly manual acquisition time t lock ? t acq +t al ? tracking mode entry frequency tolerance d trk 0? 3.6% acquisition mode entry frequency tolerance d unt 6.3% ? 7.2% lock entry freq. tolerance d lock 0? 0.9% lock exit freq. tolerance d unl 0.9% ? 1.8% reference cycles per acquisition mode measurement n acq ?32? reference cycles per tracking mode measurement n trk ?128? automatic mode time to stable t acq n acq /f xclk (8 v dda )/(f xclk k acq) if c f chosen correctly automatic stable to lock time t al n trk /f xclk (4 v dda )/(f xclk k trk ) ? if c f chosen correctly automatic lock time t lock ? t acq + t al ? pll jitter, deviation of average bus frequency over 2 ms 0? (f crys ) (.025%) (n/4) n = vco freq. mult. (gbnt) (2) 2. gbnt guaranteed but not tested.
electrical specifications mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor electrical specifications 385 23.13 flash memory characteristics characteristic symbol min max unit flash program bus clock frequency ? 1 ? mhz flash read bus clock frequency f read (1) notes : 1. f read is defined as the frequency range for which the flash memory can be read. 32k 8.4m hz flash page erase time t erase (2) 2. if the page erase time is longer than t erase (min), there is no erase- disturb, but it reduces the endurance of the flash memory. 1?ms flash mass erase time t merase (3) 3. if the mass erase time is longer than t merase (min), there is no erase-disturb, but it reduces the endurance of the flash memory. 4?ms flash pgm/erase to hven set up time t nvs 10 ? s flash high-voltage hold time t nvh 5? s flash high-voltage hold time (mass erase) t nvhl 100 ? s flash program hold time t pgs 5? s flash program time t prog 30 40 s flash return to read time t rcv (4) 4. t rcv is defined as the time it needs before the flash can be read after turning off the high voltage charge pump, by clearing hven to logic 0. 1? s flash cumulative program hv period t hv (5) 5. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog 64) t hv max. ?4 ms flash row erase endurance (6) 6. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase / program cycles. ? 10,000 ? cycles flash row program endurance (7) 7. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase / program cycles. ? 10,000 ? cycles flash data retention time (8) 8. the flash is guaranteed to retain data over the entire operating temper ature range for at least the minimum time specified. ?10?years
electrical specifications technical data mc68hc908ab32 ? rev. 1.1 386 electrical specifications freescale semiconductor
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor mechanical specifications 387 technical data ? mc68hc908ab32 section 24. mechanical specifications 24.1 contents 24.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 24.3 64-pin plastic quad flat pack (qfp) . . . . . . . . . . . . . . . . . . . 388 24.2 introduction this section gives t he dimensions for: 64-pin plastic quad fl at pack (case 840b-01) figure 24-1 shows the latest package dra wing at the time of this publication. to make sure that you have the latest package specifications, please visi t the freescale website at http://freescale.com. follow the world wide web on-line inst ructions to retrieve the current mechanical specifications.
mechanical specifications technical data mc68hc908ab32 ? rev. 1.1 388 mechanical specifications freescale semiconductor 24.3 64-pin plastic quad flat pack (qfp) figure 24-1. 64-pin plasti c quad flat pack (qfp) l l ?a? ?b? detail a ?d? b a s v detail a p b b d ?a?, ?b?, ?d? c ?c? e h g m m detailc seating plane datum plane 1 16 ?h? 0.01 (0.004) r detail c datum plane ?h? t u q k w x s a?b m 0.20 (0.008) d s h s a?b m 0.20 (0.008) d s c 0.05 (0.002) a?b s a?b m 0.20 (0.008) d s c 0.05 (0.002) a?b s a?b m 0.20 (0.008) d s h 48 33 s a?b m 0.02 (0.008) d s c n f j base metal 32 49 17 64 dim min max min max inches millimeters a 13.90 14.10 0.547 0.555 b 13.90 14.10 0.547 0.555 c 2.15 2.45 0.085 0.096 d 0.30 0.45 0.012 0.018 e 2.00 2.40 0.079 0.094 f 0.30 0.40 0.012 0.016 g 0.80 bsc 0.031 bsc h ? 0.25 ? 0.010 j 0.13 0.23 0.005 0.009 k 0.65 0.95 0.026 0.037 l 12.00 ref 0.472 ref m 5 10 5 10 n 0.13 0.17 0.005 0.007 p 0.40 bsc 0.016 bsc q 0 7 0 7 r 0.13 0.30 0.005 0.012 s 16.95 17.45 0.667 0.687 t 0.13 ? 0.005 ? u 0 ?0 ? v 16.95 17.45 0.667 0.687 w 0.35 0.45 0.014 0.018 x 1.6 ref 0.063 ref notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?h? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?a?, ?b? and ?d? to be determined at datum plane ?h?. 5. dimensions s and v to be determined at seating plane ?c?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?h?. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) per side. total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. section b?b
mc68hc908ab32 ? rev. 1.1 technical data freescale semiconductor ordering information 389 technical data ? mc68hc908ab32 section 25. ordering information 25.1 contents 25.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 25.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 25.2 introduction this section contains ordering numbers for the mc68hc908ab32. 25.3 mc order numbers table 25-1. mc order numbers mc order number (1) notes : 1. fu = quad flat pack c = operating temperature range: ?40 c to +85 c m = operating temperature range: ?40 c to +125 c operating temperature range MC68HC908AB32CFU ?40 c to +85 c mc68hc908ab32mfu ?40 c to +125 c
ordering information technical data mc68hc908ab32 ? rev. 1.1 390 ordering information freescale semiconductor

how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the arm powered logo is a registered trademark of arm limited. arm7tdmi-s is a trademark of arm limited. java and all other java-based marks are trademarks or registered trademarks of sun microsystems, inc. in the u.s. and other countries. the bluetooth trademarks are owned by their proprietor and used by freescale semiconductor, inc. under license. ? freescale semiconductor, inc. 2005. all rights reserved. rev. 1.1 mc68hc908ab32/d august 2, 2005

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